Usage: /usr/x86_64-pc-linux-gnu/bin/as [option...] [asmfile...] Options: -a[sub-option...] turn on listings Sub-options [default hls]: c omit false conditionals d omit debugging directives g include general info h include high-level source i include ginsn and synthesized CFI info l include assembly m include macro expansions n omit forms processing s include symbols =FILE list to FILE (must be last sub-option) --alternate initially turn on alternate macro syntax --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi|zstd}] compress DWARF debug sections Default: zlib --nocompress-debug-sections don't compress DWARF debug sections -D produce assembler debugging messages --dump-config display how the assembler is configured and then exit --debug-prefix-map OLD=NEW map OLD to NEW in debug information --defsym SYM=VAL define symbol SYM to given value --execstack require executable stack for this object --noexecstack don't require executable stack for this object --size-check=[error|warning] ELF .size directive check (default --size-check=error) --elf-stt-common=[no|yes] (default: no) generate ELF common symbols with STT_COMMON type --sectname-subst enable section name substitution sequences --generate-missing-build-notes=[no|yes] (default: no) generate GNU Build notes if none are present in the input --gsframe[={no|yes}] whether to generate SFrame stack trace information (default: no) Default version emitted is V3 --gsframe- generate SFrame version information. 3 == --reloc-section-sym=[all|internal|none] adjust eligible relocations to use section symbols (default: all) --scfi=experimental Synthesize DWARF CFI for hand-written asm (experimental support) -f skip whitespace and comment preprocessing -g, --gen-debug generate debugging information --gstabs generate STABS debugging information --gstabs+ generate STABS debug info with GNU extensions --gdwarf- generate DWARF debugging information. 2 <= <= 5 --gdwarf-cie-version= generate version 1, 3 or 4 DWARF CIEs --gdwarf-sections generate per-function section names for DWARF line information --hash-size= ignored --help show all assembler options --target-help show target specific options -I DIR add DIR to search list for .include directives -J don't warn about signed overflow -K warn when differences altered for long displacements -L, --keep-locals keep local symbols (e.g. starting with `L') -M, --mri assemble in MRI compatibility mode --MD FILE write dependency information in FILE (default none) --multibyte-handling= what to do with multibyte characters encountered in the input -nocpp ignored -no-pad-sections do not pad the end of sections to alignment boundaries -o OBJFILE name the object-file output OBJFILE (default a.out) -R fold data section into text section --reduce-memory-overheads ignored --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --traditional-format Use same format as native assembler when possible --version print assembler version number and exit -W, --no-warn suppress warnings --warn don't suppress warnings --fatal-warnings treat warnings as errors --no-info suppress information messages --info don't suppress information messages -w ignored -X ignored -Z generate object file even after errors --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing @FILE read options from FILE -Qy, -Qn ignored -V print assembler version number -k ignored -n do not optimize code alignment -O{012s} attempt some code optimizations -q quieten some warnings -s ignored --32/--64/--x32 generate 32bit/64bit/x32 object --divide ignored -march=CPU[,+EXTENSION...] generate code for CPU and EXTENSION, CPU is one of: default, push, pop, generic32, generic64, i386, i486, i586, pentium, i686, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2 EXTENSION is combination of (possibly "no"-prefixed): 8087, 287, 387, 687, cmov, fxsr, mmx, sse, sse2, sse3, sse4a, ssse3, sse4.1, sse4.2, sse4, avx, avx2, avx512f, avx512cd, avx512er, avx512pf, avx512dq, avx512bw, avx512vl, monitor, vmx, vmfunc, smx, xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c, bmi2, fma, fma4, xop, lwp, movbe, cx16, lahf_sahf, ept, lzcnt, popcnt, hle, rtm, tsx, invpcid, clflush, nop, syscall, rdtscp, 3dnow, 3dnowa, padlock, svme, abm, bmi, tbm, adx, rdseed, prfchw, smap, mpx, sha, clflushopt, prefetchwt1, se1, clwb, avx512ifma, avx512vbmi, avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2, avx512_vnni, avx512_bitalg, avx_vnni, clzero, mwaitx, ospke, rdpid, ptwrite, ibt, shstk, gfni, vaes, vpclmulqdq, wbnoinvd, pconfig, waitpkg, cldemote, amx_int8, amx_bf16, amx_fp16, amx_complex, amx_transpose, amx_tf32, amx_fp8, amx_movrs, amx_avx512, amx_tile, movdiri, movdir64b, avx512_bf16, avx512_vp2intersect, avx512_bmm, tdx, enqcmd, serialize, rdpru, mcommit, sev_es, tsxldtrk, kl, widekl, uintr, hreset, avx512_fp16, prefetchi, avx_ifma, avx_vnni_int8, cmpccxadd, wrmsrns, msrlist, avx_ne_convert, rao_int, rmpquery, rmpread, fred, lkgs, avx_vnni_int16, sha512, sm3, sm4, pbndkb, avx10.1, user_msr, apx_f, apx_nci, apx_ndd, apx_nf, apx_nci_ndd_nf, avx10.2, gmism2, gmiccs, msr_imm, padlockrng2, padlockphe2, padlockxmodx, movrs, no87 -mtune=CPU optimize for CPU, CPU is one of: generic32, generic64, i8086, i186, i286, i386, i486, i586, pentium, i686, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, znver5, znver6, btver1, btver2 -msse2avx encode SSE instructions with VEX prefix -muse-unaligned-vector-move encode aligned vector move as unaligned vector move -msse-check=[none|error|warning] (default: none) check SSE instructions -moperand-check=[none|error|warning] (default: warning) check operand combinations for validity -mavxscalar=[128|256] (default: 128) encode scalar AVX instructions with specific vector length -mvexwig=[0|1] (default: 0) encode VEX instructions with specific VEX.W value for VEX.W bit ignored instructions -mevexlig=[128|256|512] (default: 128) encode scalar EVEX instructions with specific vector length -mevexwig=[0|1] (default: 0) encode EVEX instructions with specific EVEX.W value for EVEX.W bit ignored instructions -mevexrcig=[rne|rd|ru|rz] (default: rne) encode EVEX instructions with specific EVEX.RC value for SAE-only ignored instructions -mmnemonic=[att|intel] (default: att) use AT&T/Intel mnemonic (AT&T syntax only) -msyntax=[att|intel] (default: att) use AT&T/Intel syntax -mindex-reg support pseudo index registers -mnaked-reg don't require `%' prefix for registers -madd-bnd-prefix add BND prefix for all valid branches -mshared disable branch optimization for shared code -mx86-used-note=[no|yes] (default: yes) generate x86 used ISA and feature properties -momit-lock-prefix=[no|yes] (default: no) strip all lock prefixes -mfence-as-lock-add=[no|yes] (default: no) encode lfence, mfence and sfence as lock addl $0x0, (%{re}sp) -mrelax-relocations=[no|yes] (default: yes) generate relax relocations -mtls-check=[no|yes] (default: yes) check TLS relocation -malign-branch-boundary=NUM (default: 0) align branches within NUM byte boundary -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp) TYPE is combination of jcc, fused, jmp, call, ret, indirect specify types of branches to align -malign-branch-prefix-size=NUM (default: 5) align branches with NUM prefixes per instruction -mbranches-within-32B-boundaries align branches within 32 byte boundary -mlfence-after-load=[no|yes] (default: no) generate lfence after load -mlfence-before-indirect-branch=[none|all|register|memory] (default: none) generate lfence before indirect near branch -mlfence-before-ret=[none|or|not|shl|yes] (default: none) generate lfence before ret -mamd64 accept only AMD64 ISA [default] -mintel64 accept only Intel64 ISA Report bugs to