OVERVIEW: llvm .bc -> .bc modular optimizer and analysis printer
USAGE: opt [options]
OPTIONS:
Color Options:
--color - Use colors in output (default=autodetect)
DXContainer Options:
--compress-srci= - Choose SCRI part compression:
=none - No compression
=zlib - Use zlib
General options:
--O0 - Optimization level 0. Similar to clang -O0. Same as -passes="default"
--O1 - Optimization level 1. Similar to clang -O1. Same as -passes="default"
--O2 - Optimization level 2. Similar to clang -O2. Same as -passes="default"
--O3 - Optimization level 3. Similar to clang -O3. Same as -passes="default"
--Os - Like -O2 but size-conscious. Similar to clang -Os. Same as -passes="default"
--Oz - Like -O2 but optimize for code size above all else. Similar to clang -Oz. Same as -passes="default"
-S - Write output as LLVM assembly
--aarch64-neon-syntax= - Choose style of NEON code to emit from AArch64 backend:
=generic - Emit generic NEON assembly
=apple - Emit Apple-style NEON assembly
--aarch64-use-aa - Enable the use of AA during codegen.
--abort-on-max-devirt-iterations-reached - Abort when the max iterations for devirtualization CGSCC repeat pass is reached
--addrsig - Emit an address-significance table
--align-loops= - Default alignment for loops
--allow-ginsert-as-artifact - Allow G_INSERT to be considered an artifact. Hack around AMDGPU test infinite loops.
--amdgpu-atomic-optimizer-strategy= - Select DPP or Iterative strategy for scan
=DPP - Use DPP operations for scan
=Iterative - Use Iterative approach for scan
=None - Disable atomic optimizer
--amdgpu-bypass-slow-div - Skip 64-bit divide for dynamic 32-bit values
--amdgpu-disable-loop-alignment - Do not align and prefetch loops
--amdgpu-dpp-combine - Enable DPP combiner
--amdgpu-dump-hsa-metadata - Dump AMDGPU HSA Metadata
--amdgpu-enable-merge-m0 - Merge and hoist M0 initializations
--amdgpu-indirect-call-specialization-threshold= - A threshold controls whether an indirect call will be specialized
--amdgpu-kernarg-preload - Enable preload kernel arguments to SGPRs
--amdgpu-kernarg-preload-count= - How many kernel arguments to preload onto SGPRs
--amdgpu-module-splitting-max-depth= - maximum search depth. 0 forces a greedy approach. warning: the algorithm is up to O(2^N), where N is the max depth.
--amdgpu-promote-alloca-to-vector-limit= - Maximum byte size to consider promote alloca to vector
--amdgpu-promote-alloca-to-vector-max-regs= - Maximum vector size (in 32b registers) to use when promoting alloca
--amdgpu-promote-alloca-to-vector-vgpr-ratio= - Ratio of VGPRs to budget for promoting alloca to vectors
--amdgpu-sdwa-peephole - Enable SDWA peepholer
--amdgpu-use-aa-in-codegen - Enable the use of AA during codegen.
--amdgpu-verify-hsa-metadata - Verify AMDGPU HSA Metadata
--amdgpu-vgpr-index-mode - Use GPR indexing mode instead of movrel for vector indexing
--arc-contract-use-objc-claim-rv - Enable generation of calls to objc_claimAutoreleasedReturnValue
--argext-abi-check - Verify that narrow int args are properly extended per the SystemZ ABI.
--arm-add-build-attributes -
--arm-implicit-it= - Allow conditional instructions outside of an IT block
=always - Accept in both ISAs, emit implicit ITs in Thumb
=never - Warn in ARM, reject in Thumb
=arm - Accept in ARM, reject in Thumb
=thumb - Warn in ARM, emit implicit ITs in Thumb
--asm-show-inst - Emit internal instruction representation to assembly file
--atomic-counter-update-promoted - Do counter update using atomic fetch add for promoted counters only
--atomic-first-counter - Use atomic fetch add for first counter in a function (usually the entry counter)
--basic-block-address-map - Emit the basic block address map section
--basic-block-section-match-infer - Enable matching and inference when generating basic block sections
--basic-block-sections= | labels | none> - Emit basic blocks into separate sections
--bounds-checking-single-trap - Use one trap block per function
--bpf-stack-size= - Specify the BPF stack size limit
--call-graph-section - Emit a call graph section
--cfg-hide-cold-paths= - Hide blocks with relative frequency below the given value
--cfg-hide-deoptimize-paths -
--cfg-hide-unreachable-paths -
--check-functions-filter= - Only emit checks for arguments of functions whose names match the given regular expression
--code-model= - Choose code model
=tiny - Tiny code model
=small - Small code model
=kernel - Kernel code model
=medium - Medium code model
=large - Large code model
--codegen-opt-level= - Override optimization level for codegen hooks, legacy PM only
--conditional-counter-update - Do conditional counter updates in single byte counters mode)
--cost-kind= - Target cost kind
=throughput - Reciprocal throughput
=latency - Instruction latency
=code-size - Code size
=size-latency - Code size and latency
=all - Print all cost kinds
--crel - Use CREL relocation format for ELF
--cs-profile-generate - Perform context sensitive PGO instrumentation
--cs-profile-path= - Context sensitive profile file path
--ctx-prof-include-empty - Also write profiles with all-zero counters. Intended for testing/debugging.
--ctx-profile-force-is-specialized - Treat the given module as-if it were containing the post-thinlink module containing the root
--data-layout= - data layout string to use
--data-sections - Emit data into separate sections
--debug-entry-values - Enable debug info for the debug entry values.
--debug-print - Print function mir after transformation
--debugger-tune= - Tune debug info for a particular debugger
=gdb - gdb
=lldb - lldb
=dbx - dbx
=sce - SCE targets (e.g. PS4)
--debugify-atoms -
--debugify-each - Start each pass with debugify and end it with check-debugify
--debugify-export= - Export per-pass debugify statistics to this file
--debugify-func-limit= - Set max number of processed functions per pass.
--debugify-level= - Kind of debug info to add
=locations - Locations only
=location+variables - Locations and Variables
--debugify-quiet - Suppress verbose debugify output
--denormal-fp-math= - Select which denormal numbers the code is permitted to require
=ieee - IEEE 754 denormal numbers
=preserve-sign - the sign of a flushed-to-zero number is preserved in the sign of 0
=positive-zero - denormals are flushed to positive zero
=dynamic - denormals have unknown treatment
--denormal-fp-math-f32= - Select which denormal numbers the code is permitted to require for float
=ieee - IEEE 754 denormal numbers
=preserve-sign - the sign of a flushed-to-zero number is preserved in the sign of 0
=positive-zero - denormals are flushed to positive zero
=dynamic - denormals have unknown treatment
--devirtualize-speculatively - Enable speculative devirtualization optimization
--disable-auto-upgrade-debug-info - Disable autoupgrade of debug info
--disable-builtin= - Disable specific target library builtin function
--disable-debug-info-type-map - Don't use a uniquing type map for debug info
--disable-handle-qfp - Disable handling of Qfloat spills/refills after register allocation.
--disable-i2p-p2i-opt - Disables inttoptr/ptrtoint roundtrip optimization
--disable-loop-unrolling - Disable loop unrolling in all relevant passes
--disable-promote-alloca-to-lds - Disable promote alloca to LDS
--disable-promote-alloca-to-vector - Disable promote alloca to vector
--disable-qfp-opt - Disable optimization of Qfloat operations.
--disable-qfp-opt-mul - Disable optimization of Qfloat operations for multiply.
--disable-simplify-libcalls - Disable simplify-libcalls
--disable-tail-calls - Never emit tail calls
--do-counter-promotion - Do counter register promotion
--dot-cfg-mssa= - file name for generated dot file
--dwarf-version= - Dwarf version
--dwarf64 - Generate debugging info in the 64-bit DWARF format
--dx-embed-debug - Embed PDB in shader container
--elide-all-zero-branch-weights -
--emit-bb-hash - Emit the hash of basic block in the SHT_LLVM_BB_ADDR_MAP section.
--emit-call-site-info - Emit call site debug information, if debug information is enabled.
--emit-compact-unwind-non-canonical - Whether to try to emit Compact Unwind for non canonical entries.
--emit-dwarf-unwind= - Whether to emit DWARF EH frame entries.
=always - Always emit EH frame entries
=no-compact-unwind - Only emit EH frame entries when compact unwind is not available
=dwarf-only - Force compact unwind to reference DWARF
=default - Use target platform default
--emscripten-cxx-exceptions-allowed= - The list of function names in which Emscripten-style exception handling is enabled (see emscripten EMSCRIPTEN_CATCHING_ALLOWED options)
--emulated-tls - Use emulated TLS model
--enable-builtin= - Enable specific target library builtin functions
--enable-cse-in-irtranslator - Should enable CSE in irtranslator
--enable-cse-in-legalizer - Should enable CSE in Legalizer
--enable-debugify - Start the pipeline with debugify and end it with check-debugify
--enable-devirtualize-speculatively - Enable speculative devirtualization optimization
--enable-emscripten-cxx-exceptions - WebAssembly Emscripten-style exception handling
--enable-emscripten-sjlj - WebAssembly Emscripten-style setjmp/longjmp handling
--enable-gvn-hoist - Enable the GVN hoisting pass (default = off)
--enable-gvn-memdep -
--enable-gvn-memoryssa -
--enable-gvn-sink - Enable the GVN sinking pass (default = off)
--enable-jmc-instrument - Instrument functions with a call to __CheckForDebuggerJustMyCode
--enable-jump-table-to-switch - Enable JumpTableToSwitch pass (default = true)
--enable-load-in-loop-pre -
--enable-load-pre -
--enable-loop-simplifycfg-term-folding -
--enable-name-compression - Enable name/filename string compression
--enable-no-trapping-fp-math - Enable setting the FP exceptions build attribute not to use exceptions
--enable-poison-reuse-guard - Enable poison-reuse guard
--enable-postra-xqf-check - Enable ABI compliance for xqf operands post regalloc.
--enable-profcheck - Start the pipeline with prof-inject and end it with prof-verify
--enable-rem-conv - Enable extraneous conversions removal
--enable-split-backedge-in-load-pre -
--enable-split-loopiv-heuristic - Enable loop iv regalloc heuristic
--enable-tlsdesc - Enable the use of TLS Descriptors
--enable-vtable-profile-use - If ThinLTO and WPD is enabled and this option is true, vtable profiles will be used by ICP pass for more efficient indirect call sequence. If false, type profiles won't be used.
--enable-vtable-value-profiling - If true, the virtual table address will be instrumented to know the types of a C++ pointer. The information is used in indirect call promotion to do selective vtable-based comparison.
--enable-xqf-gen - Enable XQFloat generations
--exception-model= - exception model
=default - default exception handling model
=dwarf - DWARF-like CFI based exception handling
=sjlj - SjLj exception handling
=arm - ARM EHABI exceptions
=wineh - Windows exception model
=wasm - WebAssembly exception handling
--expand-variadics-override= - Override the behaviour of expand-variadics
=unspecified - Use the implementation defaults
=disable - Disable the pass entirely
=optimize - Optimise without changing ABI
=lowering - Change variadic calling convention
--experimental-debug-variable-locations - Use experimental new value-tracking variable locations
-f - Enable binary output on terminals
--fatal-warnings - Treat warnings as errors
--fdpic - Use the FDPIC ABI
--filetype= - Choose a file type (not all types are supported by all targets):
=asm - Emit an assembly ('.s') file
=obj - Emit a native object ('.o') file
=null - Emit nothing, for performance testing
--float-abi= - Choose float ABI type
=default - Target default float ABI type
=soft - Soft float ABI (implied by -soft-float)
=hard - Hard float ABI (uses FP registers)
--force-dwarf-frame-section - Always emit a debug frame section.
--force-tail-folding-style= - Force the tail folding style
=none - Disable tail folding
=data - Create lane mask for data only, using active.lane.mask intrinsic
=data-without-lane-mask - Create lane mask with compare/stepvector
=data-and-control - Create lane mask using active.lane.mask intrinsic, and use it for both data and control flow
=data-with-evl - Use predicated EVL instructions for tail folding. If EVL is unsupported, fallback to data-without-lane-mask.
--fp-contract= - Enable aggressive formation of fused FP ops
=fast - Fuse FP ops whenever profitable
=on - Only fuse 'blessed' FP ops.
=off - Only fuse FP ops when the result won't be affected.
--frame-pointer= - Specify frame pointer elimination optimization
=all - Disable frame pointer elimination
=non-leaf - Disable frame pointer elimination for non-leaf frame but reserve the register in leaf functions
=non-leaf-no-reserve - Disable frame pointer elimination for non-leaf frame
=reserved - Enable frame pointer elimination, but reserve the frame pointer register
=none - Enable frame pointer elimination
--fs-profile-debug-bw-threshold= - Only show debug message if the source branch weight is greater than this value.
--fs-profile-debug-prob-diff-threshold= - Only show debug message if the branch probability is greater than this value (in percentage).
--function-sections - Emit functions into separate sections
--generate-merged-base-profiles - When generating nested context-sensitive profiles, always generate extra base profile for function with all its context profiles merged into it.
--gpsize= - Global Pointer Addressing Size. The default size is 8.
--gsframe - Whether to emit .sframe unwind sections.
--hash-based-counter-split - Rename counter variable of a comdat function based on cfg hash
--hexagon-add-build-attributes -
--hexagon-rdf-limit= -
--hot-cold-split - Enable hot-cold splitting pass
--hwasan-percentile-cutoff-hot= - Hot percentile cutoff.
--hwasan-random-rate= - Probability value in the range [0.0, 1.0] to keep instrumentation of a function. Note: instrumentation can be skipped randomly OR because of the hot percentile cutoff, if both are supplied.
--ignore-xcoff-visibility - Not emit the visibility attribute for asm in AIX OS or give all symbols 'unspecified' visibility in XCOFF object file
--implicit-mapsyms - Allow mapping symbol at section beginning to be implicit, lowering number of mapping symbols at the expense of some portability. Recommended for projects that can build all their object files using this option
--import-all-index - Import all external functions in index.
--incremental-linker-compatible - When used with filetype=obj, emit an object file which can be used with an incremental linker
--instcombine-code-sinking - Enable code sinking
--instcombine-guard-widening-window= - How wide an instruction window to bypass looking for another guard
--instcombine-max-num-phis= - Maximum number phis to handle in intptr/ptrint folding
--instcombine-max-sink-users= - Maximum number of undroppable users for instruction sinking
--instcombine-maxarray-size= - Maximum array size considered when doing a combine
--instcombine-negator-enabled - Should we attempt to sink negations?
--instcombine-negator-max-depth= - What is the maximal lookup depth when trying to check for viability of negation sinking.
--instrprof-atomic-counter-update-all - Make all profile counter updates atomic (for testing only)
--instrumentor-read-config-files= - Read the instrumentor configuration from the specified JSON files (comma separated)
--instrumentor-read-config-paths-file= - Read the instrumentor configuration file paths from the specified file (newline separated)
--instrumentor-write-config-file= - Write the instrumentor configuration into the specified JSON file
--internalize-public-api-file= - A file containing list of symbol names to preserve
--internalize-public-api-list= - A list of symbol names to preserve
--intrinsic-cost-strategy= - Costing strategy for intrinsic instructions
=instruction-cost - Use TargetTransformInfo::getInstructionCost
=intrinsic-cost - Use TargetTransformInfo::getIntrinsicInstrCost
=type-based-intrinsic-cost - Calculate the intrinsic cost based only on argument types
--iterative-counter-promotion - Allow counter promotion across the whole loop nest.
--large-data-threshold= - Choose large data threshold for x86_64 medium code model
--large-eh-encoding - Force 8-byte (sdata8) pointer encodings for ELF exception-handling sections to avoid relocation overflows in large binaries (x86_64: FDE/personality/LSDA/TType; AArch64/PPC64: FDE only, the rest are already sdata8)
--load= - Load the specified plugin
--load-pass-plugin= - Load passes from plugin library
--loongarch-use-aa - Enable the use of AA during codegen.
--lower-allow-check-percentile-cutoff-hot= - Hot percentile cutoff.
--lower-allow-check-random-rate= - Probability value in the range [0.0, 1.0] of unconditional pseudo-random checks.
--lto-aix-system-assembler= - Path to a system assembler, picked up on AIX only
--lto-embed-bitcode= - Embed LLVM bitcode in object files produced by LTO
=none - Do not embed
=optimized - Embed after all optimization passes
=post-merge-pre-opt - Embed post merge, but before optimizations
--lto-pass-remarks-filter= - Only record optimization remarks from passes whose names match the given regular expression
--lto-pass-remarks-format= - The format used for serializing remarks (default: YAML)
--lto-pass-remarks-output= - Output filename for pass remarks
--march= - Architecture to generate code for (see --version)
--matrix-default-layout= - Sets the default matrix layout
=column-major - Use column-major layout
=row-major - Use row-major layout
--matrix-print-after-transpose-opt -
--mattr= - Target specific attributes (-mattr=help for details)
--max-counter-promotions= - Max number of allowed counter promotions
--max-counter-promotions-per-loop= - Max number counter promotions per loop to avoid increasing register pressure too much
--mc-relax-all - When used with filetype=obj, relax all fixups in the emitted object file
--mcabac - tbd
--mcpu= - Target a specific cpu type (-mcpu=help for details)
--meabi= - Set EABI type (default depends on triple):
=default - Triple default EABI version
=4 - EABI version 4
=5 - EABI version 5
=gnu - EABI GNU
--merror-missing-parenthesis - Error for missing parenthesis around predicate registers
--merror-noncontigious-register - Error for register names that aren't contigious
--mhvx - Enable Hexagon Vector eXtensions
--mhvx= - Enable Hexagon Vector eXtensions
=v60 - Build for HVX v60
=v62 - Build for HVX v62
=v65 - Build for HVX v65
=v66 - Build for HVX v66
=v67 - Build for HVX v67
=v68 - Build for HVX v68
=v69 - Build for HVX v69
=v71 - Build for HVX v71
=v73 - Build for HVX v73
=v75 - Build for HVX v75
=v79 - Build for HVX v79
=v81 - Build for HVX v81
--mips-compact-branches= - MIPS Specific: Compact branch policy.
=never - Do not use compact branches if possible.
=optimal - Use compact branches where appropriate (default).
=always - Always use compact branches if possible.
--mips16-constant-islands - Enable mips16 constant islands.
--mips16-hard-float - Enable mips16 hard float.
--mir-strip-debugify-only - Should mir-strip-debug only strip debug info from debugified modules by default
--misexpect-tolerance= - Prevents emitting diagnostics when profile counts are within N% of the threshold..
--mno-compound - Disable looking for compound instructions for Hexagon
--mno-fixup - Disable fixing up resolved relocations for Hexagon
--mno-ldc1-sdc1 - Expand double precision loads and stores to their single precision counterparts
--mno-pairing - Disable looking for duplex instructions for Hexagon
--module-hash - Emit module hash
--module-summary - Emit module summary index
--ms-secure-hotpatch-functions-file= - A file containing list of mangled function names to mark for Windows Secure Hot-Patching
--ms-secure-hotpatch-functions-list= - A list of mangled function names to mark for Windows Secure Hot-Patching
--mtriple= - Override target triple for module
--mtune= - Tune for a specific CPU microarchitecture (-mtune=help for details)
--mwarn-missing-parenthesis - Warn for missing parenthesis around predicate registers
--mwarn-noncontigious-register - Warn for register names that aren't contigious
--mwarn-sign-mismatch - Warn for mismatching a signed and unsigned value
--mxcoff-roptr - When set to true, const objects with relocatable address values are put into the RO data section.
--no-deprecated-warn - Suppress all deprecated warnings
--no-discriminators - Disable generation of discriminator information.
--no-integrated-as - Disable integrated assembler
--no-type-check - Suppress type errors (Wasm)
--no-warn - Suppress all warnings
--nozero-initialized-in-bss - Don't place zero-initialized symbols into bss section
--nvptx-approx-log2f32 - NVPTX Specific: whether to use lg2.approx for log2
--nvptx-sched4reg - NVPTX Specific: schedule for register pressue
-o - Override output filename
--object-size-offset-visitor-max-visit-instructions= - Maximum number of instructions for ObjectSizeOffsetVisitor to look at
--offload-pgo-sampling= - Log2 of the sampling period for offload PGO instrumentation. Only 1 in every 2^N blocks is instrumented. 0 = all blocks, 1 = 50%, 2 = 25%, 3 = 12.5% (default). Higher values reduce overhead at the cost of sparser profiles.
--partition-static-data-sections - Partition data sections using profile information.
--pass-remarks-filter= - Only record optimization remarks from passes whose names match the given regular expression
--pass-remarks-format= - The format used for serializing remarks (default: YAML)
--pass-remarks-output= - Output filename for pass remarks
--passes= - A textual (comma separated) description of the pass pipeline e.g.,-passes="foo,bar", to have analysis passes available before a pass, add "require". See https://llvm.org/docs/NewPassManager.html#invoking-opt for more details on the pass pipeline syntax.
--pgo-block-coverage - Use this option to enable basic block coverage instrumentation
--pgo-temporal-instrumentation - Use this option to enable temporal instrumentation
--pgo-view-block-coverage-graph - Create a dot file of CFGs with block coverage inference information
--print-passes - Print available passes that can be specified in -passes=foo and exit
--print-pipeline-passes= - Print string describing the pipeline (best-effort only).
- =text Print a '-passes' compatible string describing the pipeline.
- =tree Print a tree-like structure describing the pipeline.
--profcheck-annotate-select - Also inject (if missing) and verify MD_prof for `select` instructions
--profcheck-default-function-entry-count= -
--profcheck-default-select-false-weight= - When annotating `select` instructions, this value will be used for the second ('false') case.
--profcheck-default-select-true-weight= - When annotating `select` instructions, this value will be used for the first ('true') case.
--profcheck-weights-for-test - Generate weights with small values for tests.
--profile-correlate= - Use debug info or binary file to correlate profiles.
= - No profile correlation
=debug-info - Use debug info to correlate
=binary - Use binary to correlate
--promote-alloca-vector-loop-user-weight= - The bonus weight of users of allocas within loop when sorting profitable allocas
--propeller-infer-threshold= - Threshold for infer stale profile
--r600-ir-structurize - Use StructurizeCFG IR pass
--reloc-section-sym= - Control section symbol conversion for relocations
=all - Use section symbols for all eligible local symbols
=internal - Only use section symbols for internal local symbols
=none - Never use section symbols
--relocation-model= - Choose relocation model
=static - Non-relocatable code
=pic - Fully relocatable, position independent code
=dynamic-no-pic - Relocatable external references, non-relocatable code
=ropi - Code and read-only data relocatable, accessed PC-relative
=rwpi - Read-write data relocatable, accessed relative to static base
=ropi-rwpi - Combination of ropi and rwpi
--riscv-add-build-attributes -
--riscv-use-aa - Enable the use of AA during codegen.
--runtime-counter-relocation - Enable relocating counters at runtime.
--safepoint-ir-verifier-print-only -
--sample-profile-check-record-coverage= - Emit a warning if less than N% of records in the input profile are matched to the IR.
--sample-profile-check-sample-coverage= - Emit a warning if less than N% of samples in the input profile are matched to the IR.
--sample-profile-max-propagate-iterations= - Maximum number of iterations to go through when propagating sample block/edge weights through the CFG.
--sampled-instr-burst-duration= - Set the profile instrumentation burst duration, which can range from 1 to the value of 'sampled-instr-period' (0 is invalid). This number of samples will be recorded for each 'sampled-instr-period' count update. Setting to 1 enables simple sampling, in which case it is recommended to set 'sampled-instr-period' to a prime number.
--sampled-instr-period= - Set the profile instrumentation sample period. A sample period of 0 is invalid. For each sample period, a fixed number of consecutive samples will be recorded. The number is controlled by 'sampled-instr-burst-duration' flag. The default sample period of 65536 is optimized for generating efficient code that leverages unsigned short integer wrapping in overflow, but this is disabled under simple sampling (burst duration = 1).
--sampled-instrumentation - Do PGO instrumentation sampling
--save-stats - Save LLVM statistics to a file in the current directory(`-save-stats`/`-save-stats=cwd`) or the directory of the outputfile (`-save-stats=obj`). (default: cwd)
--save-stats= - Save LLVM statistics to a file in the current directory(`-save-stats`/`-save-stats=cwd`) or the directory of the outputfile (`-save-stats=obj`). (default: cwd)
=cwd - Save to the current working directory
=obj - Save to the output file directory
--save-temp-labels - Don't discard temporary labels
--separate-named-sections - Use separate unique sections for named sections
--skip-ret-exit-block - Suppress counter promotion if exit blocks contain ret.
--speculative-counter-promotion-max-exiting= - The max number of exiting blocks of a loop to allow speculative counter promotion
--speculative-counter-promotion-to-loop - When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region.
--spirv-emit-op-names - Emit OpName for all instructions
--spirv-ext= - Specify list of enabled SPIR-V extensions
--spirv-fp-contract= - Override FP contraction policy for SPIR-V kernel entry points
=on - Follow IR metadata (default)
=off - Force ContractionOff on all kernel entry points
=fast - Suppress ContractionOff on all kernel entry points
--split-machine-functions - Split out cold basic blocks from machine functions based on profile information
--spv-allow-unknown-intrinsics[=] - Emit unknown intrinsics as calls to external functions. A comma-separated input list of intrinsic prefixes must be provided, and only intrinsics carrying a listed prefix get emitted as described.
--spv-dump-deps - Dump MIR with SPIR-V dependencies info
--spv-emit-nonsemantic-debug-info - Deprecated. Use -g to emit SPIR-V NonSemantic.Shader.DebugInfo instructions
--stack-size-section - Emit a section containing stack size metadata
--stack-symbol-ordering - Order local stack symbols.
--stackrealign - Force align the stack to the minimum alignment
--strict-dwarf - use strict dwarf
--strip-debug - Strip debugger symbol info from translation unit
--strip-named-metadata - Strip module-level named metadata
--summary-file= - The summary file to use for function importing.
--sve-tail-folding= - Control the use of vectorisation using tail-folding for SVE where the option is specified in the form (Initial)[+(Flag1|Flag2|...)]:
disabled (Initial) No loop types will vectorize using tail-folding
default (Initial) Uses the default tail-folding settings for the target CPU
all (Initial) All legal loop types will vectorize using tail-folding
simple (Initial) Use tail-folding for simple loops (not reductions or recurrences)
reductions Use tail-folding for loops containing reductions
noreductions Inverse of above
recurrences Use tail-folding for loops containing fixed order recurrences
norecurrences Inverse of above
reverse Use tail-folding for loops requiring reversed predicates
noreverse Inverse of above
--swift-async-fp= - Determine when the Swift async frame pointer should be set
=auto - Determine based on deployment target
=always - Always set the bit
=never - Never set the bit
--tail-predication= - MVE tail-predication pass options
=disabled - Don't tail-predicate loops
=enabled-no-reductions - Enable tail-predication, but not for reduction loops
=enabled - Enable tail-predication, including reduction loops
=force-enabled-no-reductions - Enable tail-predication, but not for reduction loops, and force this which might be unsafe
=force-enabled - Enable tail-predication, including reduction loops, and force this which might be unsafe
--tailcallopt - Turn fastcc calls into tail calls by (potentially) changing ABI.
--target-abi= - The name of the ABI to be targeted from the backend.
--thin-link-bitcode-file= - A file in which to write minimized bitcode for the thin link only
--thinlto-assume-merged - Assume the input has already undergone ThinLTO function importing and the other pre-optimization pipeline changes.
--thinlto-bc - Write output as ThinLTO-ready bitcode
--thinlto-split-lto-unit - Enable splitting of a ThinLTO LTOUnit
--thread-model= - Choose threading model
=posix - POSIX thread model
=single - Single thread model
--threads= -
--time-trace - Record time trace
--time-trace-file= - Specify time trace file destination
--tls-size= - Bit size of immediate TLS offsets
--translator-compatibility-mode - SPIR-V Translator compatibility mode
--unique-basic-block-section-names - Give unique names to every basic block section
--unique-section-names - Give unique names to every section
--use-ctors - Use .ctors instead of .init_array.
--use-undef - Use undef when generating programs.
--vec-extabi - Enable the AIX Extended Altivec ABI.
--verify-atomic-counter-promoted - Check that all profile counter updates were made atomic; no-op if atomic updates are not requested (-fprofile-update=atomic)
--verify-debuginfo-preserve - Start the pipeline with collecting and end it with checking of debug info preservation.
--verify-di-preserve-export= - Export debug info preservation failures into specified (JSON) file (should be abs path as we use append mode to insert new JSON objects)
--verify-each - Verify after each transform
--verify-each-debuginfo-preserve - Start each pass with collecting and end it with checking of debug info preservation.
--verify-region-info - Verify region info (time consuming)
--vp-counters-per-site= - The average number of profile counters allocated per value profiling site.
--vp-static-alloc - Do static counter allocation for value profiler
--wasm-enable-eh - WebAssembly exception handling
--wasm-enable-sjlj - WebAssembly setjmp/longjmp handling
--wasm-use-legacy-eh - WebAssembly exception handling (legacy)
--x86-align-branch= - Specify types of branches to align (plus separated list of types):
jcc indicates conditional jumps
fused indicates fused conditional jumps
jmp indicates direct unconditional jumps
call indicates direct and indirect calls
ret indicates rets
indirect indicates indirect unconditional jumps
--x86-align-branch-boundary= - Control how the assembler should align branches with NOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value 0 does not align branches.
--x86-branches-within-32B-boundaries - Align selected instructions to mitigate negative performance impact of Intel's micro code update for errata skx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution.
--x86-enable-apx-for-relocation - Enable APX features (EGPR, NDD and NF) for instructions with relocations on x86-64 ELF
Optimizations available (use "-passes=" for the new pass manager)
--Arm64ECCallLowering - AArch64Arm64ECCallLowering
--X86-postlegalizer-combiner - Combine X86 MachineInstrs after legalization
--aa - Function Alias Analysis Results
--aarch64-O0-prelegalizer-combiner - Combine AArch64 machine instrs before legalization
--aarch64-a57-fp-load-balancing - AArch64 A57 FP Load-Balancing
--aarch64-asm-printer - AArch64 Assembly Printer
--aarch64-branch-targets - AArch64 Branch Targets
--aarch64-ccmp - AArch64 CCMP Pass
--aarch64-code-layout-opt - AArch64 Code Layout Optimization
--aarch64-collect-loh - AArch64 Collect Linker Optimization Hint (LOH)
--aarch64-cond-br-tuning - AArch64 Conditional Branch Tuning
--aarch64-condopt - AArch64 CondOpt Pass
--aarch64-copyelim - AArch64 redundant copy elimination pass
--aarch64-dead-defs - AArch64 Dead register definitions
--aarch64-expand-pseudo - AArch64 pseudo instruction expansion pass
--aarch64-falkor-hwpf-fix - Falkor HW Prefetch Fix
--aarch64-falkor-hwpf-fix-late - Falkor HW Prefetch Fix Late Phase
--aarch64-fix-cortex-a53-835769-pass - AArch64 fix for A53 erratum 835769
--aarch64-isel - AArch64 Instruction Selection
--aarch64-jump-tables - AArch64 compress jump tables pass
--aarch64-ldst-opt - AArch64 load / store optimization pass
--aarch64-local-dynamic-tls-cleanup - AArch64 Local Dynamic TLS Access Clean-up
--aarch64-lower-homogeneous-prolog-epilog - AArch64 homogeneous prolog/epilog lowering pass
--aarch64-machine-sme-abi - Machine SME ABI
--aarch64-mi-peephole-opt - AArch64 MI Peephole Optimization
--aarch64-post-coalescer - AArch64 Post Coalescer Pass
--aarch64-post-select-optimize - Optimize AArch64 selected instructions
--aarch64-postlegalizer-combiner - Combine AArch64 MachineInstrs after legalization
--aarch64-postlegalizer-lowering - Lower AArch64 MachineInstrs after legalization
--aarch64-prelegalizer-combiner - Combine AArch64 machine instrs before legalization
--aarch64-promote-const - AArch64 Promote Constant Pass
--aarch64-ptrauth - AArch64 Pointer Authentication
--aarch64-redundantcondbranch - AArch64 Redundant Conditional Branch Elimination pass
--aarch64-simd-instr-opt - AArch64 SIMD instructions optimization pass
--aarch64-simd-scalar - AdvSIMD Scalar Operation Optimization
--aarch64-sls-hardening - AArch64 sls hardening pass
--aarch64-sme-peephole-opt - SME Peephole Optimization
--aarch64-speculation-hardening - AArch64 speculation hardening pass
--aarch64-srlt-define-superregs - AArch64 SRLT Define Super-Regs Pass
--aarch64-stack-tagging - AArch64 Stack Tagging
--aarch64-stack-tagging-pre-ra - AArch64 Stack Tagging PreRA Pass
--aarch64-stp-suppress - AArch64 Store Pair Suppression
--aarch64-sve-intrinsic-opts - SVE intrinsics optimizations
--aarch64-sve-shuffle-opts - SVE Shuffle Optimizations
--alloca-hoisting - Hoisting alloca instructions in non-entry blocks to the entry block
--always-inline - Inliner for always_inline functions
--amdgpu-aa - AMDGPU Address space based Alias Analysis
--amdgpu-aa-wrapper - AMDGPU Address space based Alias Analysis Wrapper
--amdgpu-always-inline - AMDGPU Inline All Functions
--amdgpu-annotate-uniform - Add AMDGPU uniform metadata
--amdgpu-asm-printer - AMDGPU Assembly Printer
--amdgpu-atomic-optimizer - AMDGPU atomic optimizations
--amdgpu-codegenprepare - AMDGPU IR optimizations
--amdgpu-export-kernel-runtime-handles - Externalize enqueued block runtime handles
--amdgpu-global-isel-divergence-lowering - AMDGPU GlobalISel divergence lowering
--amdgpu-image-intrinsic-opt - AMDGPU Image Intrinsic Optimizer
--amdgpu-insert-delay-alu - AMDGPU Insert Delay ALU
--amdgpu-isel - AMDGPU DAG->DAG Pattern Instruction Selection
--amdgpu-late-codegenprepare - AMDGPU IR late optimizations
--amdgpu-lower-buffer-fat-pointers - Lower buffer fat pointer operations to buffer resources
--amdgpu-lower-ctor-dtor - Lower ctors and dtors for AMDGPU
--amdgpu-lower-exec-sync - AMDGPU lowering of execution synchronization
--amdgpu-lower-intrinsics - AMDGPU lower intrinsics
--amdgpu-lower-kernel-arguments - AMDGPU Lower Kernel Arguments
--amdgpu-lower-kernel-attributes - AMDGPU Kernel Attributes
--amdgpu-lower-module-lds - Lower uses of LDS variables from non-kernel functions
--amdgpu-lower-vgpr-encoding - AMDGPU Lower VGPR Encoding
--amdgpu-mark-last-scratch-load - AMDGPU Mark last scratch load
--amdgpu-next-use-analysis - Next Use Analysis
--amdgpu-next-use-printer - AMDGPU Next Use Analysis Printer
--amdgpu-nsa-reassign - GCN NSA Reassign
--amdgpu-perf-hint - Analysis if a function is memory bound
--amdgpu-postlegalizer-combiner - Combine AMDGPU machine instrs after legalization
--amdgpu-pre-ra-long-branch-reg - AMDGPU Pre-RA Long Branch Reg
--amdgpu-pre-ra-optimizations - Pre-RA optimizations
--amdgpu-prelegalizer-combiner - Combine AMDGPU machine instrs before legalization
--amdgpu-preload-kern-arg-prolog - AMDGPU Preload Kernel Arguments Prolog
--amdgpu-preload-kernel-arguments - AMDGPU Preload Kernel Arguments
--amdgpu-prepare-agpr-alloc - AMDGPU Prepare AGPR Alloc
--amdgpu-print-rp -
--amdgpu-printf-runtime-binding - AMDGPU Printf lowering
--amdgpu-promote-alloca - AMDGPU promote alloca to vector or LDS
--amdgpu-promote-kernel-arguments - AMDGPU Promote Kernel Arguments
--amdgpu-regbank-combiner - Combine AMDGPU machine instrs after regbankselect
--amdgpu-regbanklegalize - AMDGPU Register Bank Legalize
--amdgpu-regbankselect - AMDGPU Register Bank Select
--amdgpu-remove-incompatible-functions - AMDGPU Remove Incompatible Functions
--amdgpu-reserve-wwm-regs - AMDGPU Reserve WWM Registers
--amdgpu-resource-usage - Function register usage analysis
--amdgpu-rewrite-agpr-copy-mfma - AMDGPU Rewrite AGPR-Copy-MFMA
--amdgpu-rewrite-out-arguments - AMDGPU Rewrite Out Arguments
--amdgpu-rewrite-undef-for-phi - Rewrite undef for PHI
--amdgpu-sw-lower-lds - AMDGPU Software lowering of LDS
--amdgpu-uniform-intrinsic-combine - AMDGPU Uniform Intrinsic Combine
--amdgpu-unify-divergent-exit-nodes - Unify divergent function exit nodes
--amdgpu-wait-sgpr-hazards - AMDGPU Insert waits for SGPR read hazards
--amdgpustructurizer - AMDGPU CFG Structurizer
--amode-opt - Optimize addressing mode
--arm-asm-printer - ARM Assembly Printer
--arm-block-placement - ARM block placement
--arm-branch-targets - ARM Branch Targets
--arm-cp-islands - ARM constant island placement and branch shortening pass
--arm-execution-domain-fix - ARM Execution Domain Fix
--arm-fix-cortex-a57-aes-1742098 - ARM fix for Cortex-A57 AES Erratum 1742098
--arm-isel - ARM Instruction Selection
--arm-ldst-opt - ARM load / store optimization pass
--arm-low-overhead-loops - ARM Low Overhead Loops pass
--arm-mve-gather-scatter-lowering - MVE gather/scattering lowering pass
--arm-mve-vpt - ARM MVE VPT block pass
--arm-mve-vpt-opts - ARM MVE TailPred and VPT Optimisations pass
--arm-parallel-dsp - Transform functions to use DSP intrinsics
--arm-prera-ldst-opt - ARM pre- register allocation load / store optimization pass
--arm-pseudo - ARM pseudo instruction expansion pass
--arm-sls-hardening - ARM sls hardening pass
--assumption-cache-tracker - Assumption Cache Tracker
--atomic-expand - Expand Atomic instructions
--avr-asm-printer - AVR Assembly Printer
--avr-expand-pseudo - AVR pseudo instruction expansion pass
--avr-isel - AVR DAG->DAG Instruction Selection
--avr-shift-expand - AVR Shift Expansion
--barrier - A No-Op Barrier Pass
--basic-aa - Basic Alias Analysis (stateless AA impl)
--basiccg - CallGraph Construction
--bbsections-profile-reader - Reads and parses a basic block sections profile.
--block-freq - Block Frequency Analysis
--bpf-asm-printer - BPF Assembly Printer
--bpf-check-and-opt-ir - BPF Check And Adjust IR
--bpf-isel - BPF DAG->DAG Pattern Instruction Selection
--bpf-mi-checking - BPF PreEmit Checking
--bpf-mi-expand-stack-arg-pseudos - BPF Stack argument psuedo expansion
--bpf-mi-pre-emit-peephole - BPF PreEmit Peephole Optimization
--bpf-mi-simplify-patchable - BPF PreEmit SimplifyPatchable
--bpf-mi-zext-elim - BPF MachineSSA Peephole Optimization For ZEXT Eliminate
--branch-prob - Branch Probability Analysis
--break-crit-edges - Break critical edges in CFG
--canon-freeze - Canonicalize Freeze Instructions in Loops
--check-debugify - Check debug info from -debugify
--check-debugify-function - Check debug info from -debugify-function
--codegenprepare - Optimize for code generation
--consthoist - Constant Hoisting
--convergence-region - SPIRV convergence regions analysis
--cseinfo - Analysis containing CSE Info
--cycles - Cycle Info Analysis
--da - Dependence Analysis
--dce - Dead Code Elimination
--deadargelim - Dead Argument Elimination
--debugify - Attach debug info to everything
--debugify-function - Attach debug info to a function
--domfrontier - Dominance Frontier Construction
--domtree - Dominator Tree Construction
--dot-callgraph - Print call graph to 'dot' file
--dot-dom - Print dominance tree of function to 'dot' file
--dot-dom-only - Print dominance tree of function to 'dot' file (with no function bodies)
--dot-postdom - Print postdominance tree of function to 'dot' file
--dot-postdom-only - Print postdominance tree of function to 'dot' file (with no function bodies)
--dot-regions - Print regions of function to 'dot' file
--dot-regions-only - Print regions of function to 'dot' file (with no function bodies)
--dse - Dead Store Elimination
--dwarf-eh-prepare - Prepare DWARF exceptions
--dxil-metadata-analysis - DXIL Module Metadata analysis
--dxil-resource-binding - DXIL Resource Binding Analysis
--dxil-resource-type - DXIL Resource Type Analysis
--dxil-resources - DXIL Resources Analysis
--early-cse - Early CSE
--early-cse-memssa - Early CSE w/ MemorySSA
--edge-bundles - Bundle Machine CFG Edges
--emitclausemarkers - R600 Emit Clause Markers
--errata-workaround - Errata workaround pass
--expand-condsets - Hexagon Expand Condsets
--expand-ir-insts - Expand IR instructions
--expand-reductions - Expand reduction intrinsics
--expand-variadics - Expand variadic functions
--external-aa - External Alias Analysis
--fix-irreducible - Convert irreducible control-flow into natural loops
--flattencfg - Flatten the CFG
--gcn-create-vopd - GCN Create VOPD Instructions
--gcn-dpp-combine - GCN DPP Combine
--generic-to-nvvm - Ensure that the global variables are in the global address space
--gisel-known-bits - Analysis for ComputingKnownBits
--global-merge - Merge global variables
--global-sched - Hexagon Global Scheduler
--globaldce - Dead Global Elimination
--globals-aa - Globals Alias Analysis
--gvn - Global Value Numbering
--handle-qfp-spills-refills - Hexagon PostRA Handle QFloat
--hcommgep - Hexagon Common GEP
--hexagon-asm-printer - Hexagon Assembly Printer
--hexagon-bit-simplify - Hexagon bit simplification
--hexagon-brelax - Hexagon Branch Relaxation
--hexagon-cext-opt - Hexagon constant-extender optimization
--hexagon-cfg - Hexagon CFG Optimizer
--hexagon-cfi - Hexagon call frame information
--hexagon-constp - Hexagon Constant Propagation
--hexagon-copy-combine - Hexagon Copy-To-Combine Pass
--hexagon-early-if - Hexagon early if conversion
--hexagon-gen-load-absolute - Hexagon Generate Load/Store Set Absolute Address Instruction
--hexagon-gen-mux - Hexagon generate mux instructions
--hexagon-gen-pred-pass - Hexagon generate predicate operations
--hexagon-hvx-save - Hexagon HVX Save Remarks
--hexagon-isel - Hexagon DAG->DAG Pattern Instruction Selection
--hexagon-live-vars - Hexagon Live Variable Analysis
--hexagon-loop-align - Hexagon LoopAlign pass
--hexagon-loop-idiom - Recognize Hexagon-specific loop idioms
--hexagon-loop-resched-pass - Hexagon Loop Rescheduling
--hexagon-mask - Hexagon mask
--hexagon-move-phicopy - Hexagon move phi copy
--hexagon-nvj - Hexagon NewValueJump
--hexagon-packetizer - Hexagon Packetizer
--hexagon-peephole - Hexagon Peephole
--hexagon-qfp-optimizer - QFP optimizer pass
--hexagon-rdf-opt - Hexagon RDF optimizations
--hexagon-split-double - Hexagon Split Double Registers
--hexagon-vc - Hexagon Vector Combine
--hexagon-vector-print - Hexagon VectorPrint pass
--hexagon-vextract - Hexagon optimize vextract
--hexagon-vlcr - Hexagon-specific predictive commoning for HVX vectors
--hexagon-widen-loads - Hexagon Load Widening
--hexagon-widen-stores - Hexagon Store Widening
--hexagon-xqfloat-generator - XQFloat Generator pass
--hexinsert - Hexagon generate "insert" instructions
--hextract - Hexagon generate "extract" instructions
--hwloops - Hexagon Hardware Loops
--hwloopsfixup - Hexagon Hardware Loops Fixup
--indirectbr-expand - Expand indirectbr instructions
--infer-address-spaces - Infer address spaces
--inline-asm-prepare - Prepare inline asm insts
--instcombine - Combine redundant instructions
--instruction-select - Select target instructions out of generic instructions
--instsimplify - Remove redundant instructions
--interleaved-access - Lower interleaved memory accesses to target specific intrinsics
--interleaved-load-combine - Combine interleaved loads into wide loads and shufflevector instructions
--ir-similarity-identifier - ir-similarity-identifier
--irtranslator - IRTranslator LLVM IR -> MI
--iv-users - Induction Variable Users
--jmc-instrumenter - Instrument function entry with call to __CheckForDebuggerJustMyCode
--kcfi - Insert KCFI indirect call checks
--lanai-asm-printer - Lanai Assembly Printer
--lanai-isel - Lanai DAG->DAG Pattern Instruction Selection
--lanai-mem-alu-combiner - Lanai memory ALU combiner pass
--lazy-block-freq - Lazy Block Frequency Analysis
--lazy-branch-prob - Lazy Branch Probability Analysis
--lazy-value-info - Lazy Value Information Analysis
--lcssa - Loop-Closed SSA Form Pass
--lcssa-verification - LCSSA Verifier
--legalize-spirv-implicit-binding - Legalize SPIR-V implicit bindings
--legalizer - Legalize the Machine IR a function's Machine IR
--libcall-lowering-info - Library Function Lowering Analysis
--licm - Loop Invariant Code Motion
--liveintervals - Live Interval Analysis
--liveregmatrix - Live Register Matrix
--livestacks - Live Stack Slot Analysis
--livevars - Live Variable Analysis
--load-store-vectorizer - Vectorize load and store instructions
--loadstore-opt - Generic memory optimizations
--localizer - Move/duplicate certain instructions close to their use
--loongarch-dead-defs - LoongArch Dead register definitions
--loongarch-expand-atomic-pseudo - LoongArch atomic pseudo instruction expansion pass
--loongarch-expand-pseudo - LoongArch pseudo instruction expansion pass
--loongarch-isel - LoongArch DAG->DAG Pattern Instruction Selection
--loongarch-merge-base-offset - LoongArch Merge Base Offset
--loongarch-opt-w-instrs - LoongArch Optimize W Instructions
--loongarch-prera-expand-pseudo - LoongArch Pre-RA pseudo instruction expansion pass
--loop-data-prefetch - Loop Data Prefetch
--loop-extract - Extract loops into new functions
--loop-extract-single - Extract at most one loop into a new function
--loop-reduce - Loop Strength Reduction
--loop-simplify - Canonicalize natural loops
--loop-term-fold - Loop Terminator Folding
--loop-unroll - Unroll loops
--loops - Natural Loop Information
--lower-global-dtors - Lower @llvm.global_dtors via `__cxa_atexit`
--loweratomic - Lower atomic intrinsics to non-atomic form
--lowerinvoke - Lower invoke and unwind, for unwindless code generators
--lowerswitch - Lower SwitchInst's to branches
--machine-block-freq - Machine Block Frequency Analysis
--machine-branch-prob - Machine Branch Probability Analysis
--machine-cycles - Machine Cycle Info Analysis
--machine-domfrontier - Machine Dominance Frontier Construction
--machine-loops - Machine Natural Loop Construction
--machine-trace-metrics - Machine Trace Metrics
--machine-uniformity - Machine Uniformity Info Analysis
--machinedomtree - MachineDominator Tree Construction
--machinepostdomtree - MachinePostDominator Tree Construction
--mem2reg - Promote Memory to Register
--memdep - Memory Dependence Analysis
--memoryssa - Memory SSA
--micromips-reduce-size - MicroMips instruction size reduce pass
--mips-asm-printer - Mips Assembly Printer
--mips-branch-expansion - Expand out of range branch instructions and fix forbidden slot hazards
--mips-delay-slot-filler - Fill delay slot for MIPS
--mips-isel - MIPS DAG->DAG Pattern Instruction Selection
--mips-postlegalizer-combiner - Combine Mips machine instrs after legalization
--mips-prelegalizer-combiner - Combine Mips machine instrs before legalization
--mips-set-machine-register-flags - Mips Set Machine Register Flags
--mips-vr4300-mulmul-fix - Mips VR4300 mulmul bugfix
--module-summary-analysis - Module Summary Analysis
--module-summary-info - Module summary info
--msp430-asm-printer - MSP430 Assembly Printer
--msp430-isel - MSP430 DAG->DAG Pattern Instruction Selection
--mve-laneinterleave - MVE lane interleaving
--mve-tail-predication - Transform predicated vector loops to use MVE tail predication
--nary-reassociate - Nary reassociation
--nvptx-aa - NVPTX Address space based Alias Analysis
--nvptx-aa-wrapper - NVPTX Address space based Alias Analysis Wrapper
--nvptx-address-folder - NVPTX Address Folder
--nvptx-asm-printer - NVPTX Assembly Printer
--nvptx-assign-valid-global-names - Assign valid PTX names to globals
--nvptx-atomic-lower - Lower atomics of local memory to simple load/stores
--nvptx-forward-params - NVPTX Forward Params
--nvptx-ir-peephole - NVPTX IR Peephole
--nvptx-isel - NVPTX DAG->DAG Pattern Instruction Selection
--nvptx-lower-aggr-copies - Lower aggregate copies, and llvm.mem* intrinsics into loops
--nvptx-lower-alloca - Lower Alloca
--nvptx-lower-args - Lower arguments (NVPTX)
--nvptx-lower-ctor-dtor - Lower ctors and dtors for NVPTX
--nvptx-lower-unreachable - Lower Unreachable
--nvptx-mark-kernel-ptrs-global - NVPTX Mark Kernel Pointers Global
--nvptx-peephole - NVPTX Peephole
--nvptx-prolog-epilog - NVPTX Prologue/Epilogue Insertion
--nvptx-proxyreg-erasure - NVPTX ProxyReg Erasure
--nvptx-set-byval-param-align - Set alignment of byval parameters (NVPTX)
--nvptx-tag-invariant-loads - NVPTX Tag Invariant Loads
--nvvm-intr-range - Add !range metadata to NVVM intrinsics.
--nvvm-reflect - Replace occurrences of __nvvm_reflect() calls with 0/1
--opt-remark-emitter - Optimization Remark Emitter
--packets - R600 Packetizer
--partially-inline-libcalls - Partially inline calls to library functions
--phi-values - Phi Values Analysis
--place-backedge-safepoints-impl - Place Backedge Safepoints
--post-inline-ee-instrument - Instrument function entry/exit with calls to e.g. mcount() (post inlining)
--postdomtree - Post-Dominator Tree Construction
--ppc-aix-asm-printer - AIX PPC Assembly Printer
--ppc-atomic-expand - PowerPC Expand Atomic
--ppc-bool-ret-to-int - Convert i1 constants to i32/i64 if they are returned
--ppc-branch-coalescing - Branch Coalescing
--ppc-branch-select - PowerPC Branch Selector
--ppc-ctrloops - PowerPC CTR loops generation
--ppc-early-ret - PowerPC Early-Return Creation
--ppc-gen-scalar-mass - Generate Scalar MASS entries
--ppc-isel - PowerPC DAG->DAG Pattern Instruction Selection
--ppc-linux-asm-printer - Linux PPC Assembly Printer
--ppc-loop-instr-form-prep - Prepare loop for ppc preferred instruction forms
--ppc-lower-massv-entries - Lower MASSV entries
--ppc-mi-peepholes - PowerPC MI Peephole Optimization
--ppc-pre-emit-peephole - PowerPC Pre-Emit Peephole
--ppc-prep-ifunc-aix - PPC Prepare for AIX IFunc lowering
--ppc-reduce-cr-ops - PowerPC Reduce CR logical Operation
--ppc-tls-dynamic-call - PowerPC TLS Dynamic Call Fixup
--ppc-toc-reg-deps - PowerPC TOC Register Dependencies
--ppc-vsx-copy - PowerPC VSX Copy Legalization
--ppc-vsx-fma-mutate - PowerPC VSX FMA Mutation
--ppc-vsx-swaps - PowerPC VSX Swap Removal
--pre-isel-intrinsic-lowering - Pre-ISel Intrinsic Lowering
--print-function - Print function to stderr
--print-module - Print module to stderr
--profile-summary-info - Profile summary info
--r600-expand-special-instrs - R600ExpandSpecialInstrs
--r600cf - R600 Control Flow Finalizer
--r600mergeclause - R600 Clause Merge
--reaching-defs-analysis - Reaching Definitions Analysis
--reargs - Remove Sign and Zero Extends for Args
--reassociate - Reassociate expressions
--regbankselect - Assign register bank of generic virtual registers
--regions - Detect single entry single exit regions
--replace-with-veclib - Replace intrinsics with calls to vector library
--rewrite-partial-reg-uses - Rewrite Partial Register Uses
--riscv-O0-prelegalizer-combiner - Combine RISC-V machine instrs before legalization
--riscv-asm-printer - RISC-V Assembly Printer
--riscv-codegenprepare - RISC-V CodeGenPrepare
--riscv-copyelim - RISC-V Redundant Copy Elimination
--riscv-dead-defs - RISC-V Dead register definitions
--riscv-expand-atomic-pseudo - RISC-V atomic pseudo instruction expansion pass
--riscv-expand-pseudo - RISC-V pseudo instruction expansion pass
--riscv-fold-mem-offset - RISC-V Fold Memory Offset
--riscv-gather-scatter-lowering - RISC-V gather/scatter lowering pass
--riscv-indirect-branch-tracking - RISC-V Indirect Branch Tracking
--riscv-insert-read-write-csr - RISC-V Insert Read/Write CSR Pass
--riscv-insert-vsetvli - RISC-V Insert VSETVLI pass
--riscv-insert-write-vxrm - RISC-V Insert Write VXRM Pass
--riscv-isel - RISC-V DAG->DAG Pattern Instruction Selection
--riscv-late-branch-opt - RISC-V Late Branch Optimisation Pass
--riscv-load-store-opt - RISC-V Load / Store Optimizer
--riscv-make-compressible - RISC-V Make Compressible
--riscv-merge-base-offset - RISC-V Merge Base Offset
--riscv-move-merge - RISC-V Zcmp move merging pass
--riscv-opt-w-instrs - RISC-V Optimize W Instructions
--riscv-post-ra-expand-pseudo - RISC-V post-regalloc pseudo instruction expansion pass
--riscv-postlegalizer-combiner - Combine RISC-V MachineInstrs after legalization
--riscv-prelegalizer-combiner - Combine RISC-V machine instrs before legalization
--riscv-prera-expand-pseudo - RISC-V Pre-RA pseudo instruction expansion pass
--riscv-prera-zilsd-opt - RISC-V pre-allocation Zilsd optimization
--riscv-promote-const - RISC-V Promote Constants
--riscv-push-pop-opt - RISC-V Zcmp Push/Pop optimization pass
--riscv-qc-relax-marking - RISC-V QC Relaxation Marking
--riscv-vector-peephole - RISC-V Fold Masks
--riscv-vl-optimizer - RISC-V VL Optimizer
--riscv-vmv0-elimination - RISC-V VMV0 Elimination
--runtime-library-info - Runtime Library Function Analysis
--safe-stack - Safe Stack instrumentation pass
--scalar-evolution - Scalar Evolution Analysis
--scalarize-masked-mem-intrin - Scalarize unsupported masked memory intrinsics
--scalarizer - Scalarize vector operations
--scev-aa - ScalarEvolution-based Alias Analysis
--scoped-noalias-aa - Scoped NoAlias Alias Analysis
--select-optimize - Optimize selects
--separate-const-offset-from-gep - Split GEPs to a variadic base and a constant offset for better CSE
--si-annotate-control-flow - Annotate SI Control Flow
--si-fix-sgpr-copies - SI Fix SGPR copies
--si-fix-vgpr-copies - SI Fix VGPR copies
--si-fold-operands - SI Fold Operands
--si-form-memory-clauses - SI Form memory clauses
--si-i1-copies - SI Lower i1 Copies
--si-insert-hard-clauses - SI Insert Hard Clauses
--si-insert-waitcnts - SI Insert Waitcnts
--si-late-branch-lowering - SI insert s_cbranch_execz instructions
--si-load-store-opt - SI Load Store Optimizer
--si-lower-control-flow - SI lower control flow
--si-lower-sgpr-spills - SI lower SGPR spill instructions
--si-lower-wwm-copies - SI Lower WWM Copies
--si-memory-legalizer - SI Memory Legalizer
--si-mode-register - Insert required mode register values
--si-opt-vgpr-liverange - SI Optimize VGPR LiveRange
--si-optimize-exec-masking - SI optimize exec mask operations
--si-optimize-exec-masking-pre-ra - SI optimize exec mask operations pre-RA
--si-peephole-sdwa - SI Peephole SDWA
--si-post-ra-bundler - SI post-RA bundler
--si-pre-allocate-wwm-regs - SI Pre-allocate WWM Registers
--si-pre-emit-peephole - SI peephole optimizations
--si-shrink-instructions - SI Shrink Instructions
--si-wqm - SI Whole Quad Mode
--simplifycfg - Simplify the CFG
--sink - Code sinking
--sjlj-eh-prepare - Prepare SjLj exceptions
--slotindexes - Slot index numbering
--slsr - Straight line strength reduction
--sparc-asm-printer - Sparc Assembly Printer
--sparc-isel - SPARC DAG->DAG Pattern Instruction Selection
--speculative-execution - Speculatively execute instructions
--spirv-asm-printer - SPIRV Assembly Printer
--spirv-cbuffer-access - SPIRV CBuffer Access
--spirv-emit-intrinsics - SPIRV emit intrinsics
--spirv-legalize-pointer-cast - SPIRV legalize pointer cast pass
--spirv-legalize-zero-size-arrays - Legalize SPIR-V zero-size arrays
--spirv-lower-ctor-dtor - SPIRV lower ctors and dtors
--spirv-module-analysis - SPIRV module analysis
--spirv-postlegalizer - SPIRV post legalizer
--spirv-prelegalizer - SPIRV pre legalizer
--spirv-prelegalizer-combiner - Combine SPIRV machine instrs before legalization
--spirv-prepare-functions - SPIRV prepare functions
--spirv-prepare-globals - SPIRV prepare global variables
--spirv-pushconstant-access - SPIRV push constant Access
--spirv-regularizer - SPIR-V Regularizer
--spirv-structurizer - structurize SPIRV
--split-const-for-sdata - Hexagon Split Const32s and Const64s
--split-region-exit-blocks - SPIRV split region exit blocks
--sroa - Scalar Replacement Of Aggregates
--stack-protector - Insert stack protectors
--stack-safety - Stack Safety Analysis
--stack-safety-local - Stack Safety Local Analysis
--static-data-profile-info - Static Data Profile Info
--structurizecfg - Structurize the CFG
--systemz-asm-printer - SystemZ Assembly Printer
--systemz-copy-physregs - SystemZ Copy Physregs
--systemz-elim-compare - SystemZ Comparison Elimination
--systemz-isel - SystemZ DAG->DAG Pattern Instruction Selection
--systemz-ld-cleanup - SystemZ Local Dynamic TLS Access Clean-up
--systemz-long-branch - SystemZ Long Branch
--systemz-post-rewrite - SystemZ Post Rewrite pass
--systemz-shorten-inst - SystemZ Instruction Shortening
--systemz-tdc - SystemZ Test Data Class optimization
--tailcallelim - Tail Call Elimination
--targetlibinfo - Target Library Information
--targetpassconfig - Target Pass Configuration
--tbaa - Type-Based Alias Analysis
--tfr-cleanup - Hexagon TFR Cleanup
--thumb2-reduce-size - Thumb2 instruction size reduce pass
--tilepreconfig - Tile Register Pre-configure
--tti - Target Transform Information
--uniformity - Uniformity Analysis
--unify-loop-exits - Fixup each natural loop to have a single exit block
--unreachable-mbb-elimination - Remove unreachable machine basic blocks
--unreachableblockelim - Remove unreachable blocks from the CFG
--ve-asm-printer - VE Assembly Printer
--ve-isel - VE DAG->DAG Pattern Instruction Selection
--vec-merger - R600 Vector Reg Merger
--verify - Module Verifier
--verify-safepoint-ir - Safepoint IR Verifier
--view-callgraph - View call graph
--view-dom - View dominance tree of function
--view-dom-only - View dominance tree of function (with no function bodies)
--view-postdom - View postdominance tree of function
--view-postdom-only - View postdominance tree of function (with no function bodies)
--view-regions - View regions of function
--view-regions-only - View regions of function (with no function bodies)
--virtregmap - Virtual Register Map
--wasm-add-missing-prototypes - Add prototypes to prototypes-less functions
--wasm-argument-move - Move ARGUMENT instructions for WebAssembly
--wasm-cfg-sort - Reorders blocks in topological order
--wasm-cfg-stackify - Insert BLOCK/LOOP/TRY/TRY_TABLE markers for WebAssembly scopes
--wasm-debug-fixup - Ensures debug_value's that have been stackified become stack relative
--wasm-eh-prepare - Prepare WebAssembly exceptions
--wasm-exception-info - WebAssembly Exception Information
--wasm-explicit-locals - Convert registers to WebAssembly locals
--wasm-fix-br-table-defaults - Removes range checks and sets br_table default targets
--wasm-fix-function-bitcasts - Fix mismatching bitcasts for WebAssembly
--wasm-fix-irreducible-control-flow - Removes irreducible control flow
--wasm-isel - WebAssembly Instruction Selection
--wasm-late-eh-prepare - WebAssembly Late Exception Preparation
--wasm-lower-br_unless - Lowers br_unless into inverted br_if
--wasm-lower-em-ehsjlj - WebAssembly Lower Emscripten Exceptions / Setjmp / Longjmp
--wasm-mclower-prepass - Collects information ahead of time for MC lowering
--wasm-mem-intrinsic-results - Optimize memory intrinsic result values for WebAssembly
--wasm-nullify-dbg-value-lists - WebAssembly Nullify DBG_VALUE_LISTs
--wasm-optimize-live-intervals - Optimize LiveIntervals for WebAssembly
--wasm-optimize-returned - Optimize calls with "returned" attributes for WebAssembly
--wasm-peephole - WebAssembly peephole optimizations
--wasm-postlegalizer-combiner - Combine WebAssembly MachineInstrs after legalization
--wasm-prelegalizer-combiner - Combine WebAssembly machine instrs before legalization
--wasm-ref-type-mem2local - Assign reference type allocas to local address space
--wasm-reg-coloring - Minimize number of registers used
--wasm-reg-numbering - Assigns WebAssembly register numbers for virtual registers
--wasm-reg-stackify - Reorder instructions to use the WebAssembly value stack
--wasm-replace-phys-regs - Replace physical registers with virtual registers
--wasm-set-p2align-operands - Set the p2align operands for WebAssembly loads and stores
--webassembly-asm-printer - WebAssembly Assmebly Printer
--win-eh-prepare - Prepare Windows exceptions
--write-bitcode - Write Bitcode
--x86-argument-stack-slot - Argument Stack Rebase
--x86-asm-printer - X86 Assembly Printer
--x86-avoid-sfb - Machine code sinking
--x86-avoid-trailing-call - X86 avoid trailing call pass
--x86-cf-opt - X86 Call Frame Optimization
--x86-cmov-conversion - X86 cmov Conversion
--x86-compress-evex - Compressing EVEX instrs when possible
--x86-domain-reassignment - X86 Domain Reassignment Pass
--x86-dyn-alloca-expander - X86 DynAlloca Expander
--x86-execution-domain-fix - X86 Execution Domain Fix
--x86-expand-pseudo - X86 pseudo instruction expansion pass
--x86-fast-pre-tile-config - Fast Tile Register Preconfigure
--x86-fast-tile-config - Fast Tile Register Configure
--x86-fixup-bw-insts - X86 Byte/Word Instruction Fixup
--x86-fixup-inst-tuning - x86-fixup-inst-tuning
--x86-fixup-leas - X86 LEA Fixup
--x86-fixup-setcc - x86-fixup-setcc
--x86-fixup-vector-constants - x86-fixup-vector-constants
--x86-flags-copy-lowering - X86 EFLAGS copy lowering
--x86-fp-stackifier - X86 FP Stackifier
--x86-isel - X86 DAG->DAG Instruction Selection
--x86-lower-amx-intrinsics - Lower AMX intrinsics
--x86-lower-amx-type - Lower AMX type for load/store
--x86-lower-tile-copy - Tile Copy Lowering
--x86-lvi-load - X86 LVI load hardening
--x86-lvi-ret - X86 LVI ret hardener
--x86-optimize-leas - X86 optimize LEA pass
--x86-partial-reduction - X86 Partial Reduction
--x86-prelegalizer-combiner - Combine X86 machine instrs before legalization
--x86-return-thunks - X86 Return Thunks
--x86-seses - X86 Speculative Execution Side Effect Suppression
--x86-slh - X86 speculative load hardener
--x86-suppress-apx-for-relocation - X86 Suppress APX features for relocation
--x86-tile-config - Tile Register Configure
--x86-wineh-unwindv2 - Analyze and emit instructions for Win64 Unwind v2
--x86-wineh-unwindv3 - Capacity check and sub-fragment splitting for Win64 Unwind v3
--x86-winehstate - Insert stores for EH state numbers
--xcore-asm-printer - XCore Assembly Printer
--xcore-isel - XCore DAG->DAG Pattern Instruction Selection
--xcore-lower-thread-local - Lower thread local variables
--x86-pad-max-prefix-size= - Maximum number of prefixes to use for padding
--x86-relax-relocations - Emit GOTPCRELX/REX_GOTPCRELX/CODE_4_GOTPCRELX instead of GOTPCREL on x86-64 ELF
--x86-sse2avx - Specify that the assembler should encode SSE instructions with VEX prefix
--xcoff-traceback-table - Emit the XCOFF traceback table
--xray-function-index - Emit xray_fn_idx section
Generic Options:
--help - Display available options (--help-hidden for more)
--help-list - Display list of available options (--help-list-hidden for more)
--version - Display the version of this program
IR2Vec Options:
--ir2vec-arg-weight= - Weight for argument embeddings
--ir2vec-kind= - IR2Vec embedding kind
=symbolic - Generate symbolic embeddings
=flow-aware - Generate flow-aware embeddings
--ir2vec-opc-weight= - Weight for opcode embeddings
--ir2vec-type-weight= - Weight for type embeddings
--ir2vec-vocab-path= - Path to the vocabulary file for IR2Vec
MIR2Vec Options:
--mir2vec-common-operand-weight= - Weight for common operand embeddings
--mir2vec-kind= - MIR2Vec embedding kind
=symbolic - Generate symbolic embeddings for MIR
--mir2vec-opc-weight= - Weight for machine opcode embeddings
--mir2vec-print-all-vocab-entries - Print all vocabulary entries including zero embeddings
--mir2vec-reg-operand-weight= - Weight for register operand embeddings
--mir2vec-vocab-path= - Path to the vocabulary file for MIR2Vec