libnvme(9) API Manual libnvme(9)

# [NAME](#NAME)

enum nvme\_feat - Features Access Shifts/Masks values

# [SYNOPSIS](#SYNOPSIS)

enum nvme\_feat {  
**NVME\_FEAT\_ARBITRATION\_BURST\_SHIFT** ,  
**NVME\_FEAT\_ARBITRATION\_BURST\_MASK** ,  
**NVME\_FEAT\_ARBITRATION\_LPW\_SHIFT** ,  
**NVME\_FEAT\_ARBITRATION\_LPW\_MASK** ,  
**NVME\_FEAT\_ARBITRATION\_MPW\_SHIFT** ,  
**NVME\_FEAT\_ARBITRATION\_MPW\_MASK** ,  
**NVME\_FEAT\_ARBITRATION\_HPW\_SHIFT** ,  
**NVME\_FEAT\_ARBITRATION\_HPW\_MASK** ,  
**NVME\_FEAT\_PWRMGMT\_PS\_SHIFT** ,  
**NVME\_FEAT\_PWRMGMT\_PS\_MASK** ,  
**NVME\_FEAT\_PWRMGMT\_WH\_SHIFT** ,  
**NVME\_FEAT\_PWRMGMT\_WH\_MASK** ,  
**NVME\_FEAT\_PWRMGMT\_IIELL\_SHIFT** ,  
**NVME\_FEAT\_PWRMGMT\_IIELL\_MASK** ,  
**NVME\_FEAT\_LBAR\_NR\_SHIFT** ,  
**NVME\_FEAT\_LBAR\_NR\_MASK** ,  
**NVME\_FEAT\_TT\_TMPTH\_SHIFT** ,  
**NVME\_FEAT\_TT\_TMPTH\_MASK** ,  
**NVME\_FEAT\_TT\_TMPSEL\_SHIFT** ,  
**NVME\_FEAT\_TT\_TMPSEL\_MASK** ,  
**NVME\_FEAT\_TT\_THSEL\_SHIFT** ,  
**NVME\_FEAT\_TT\_THSEL\_MASK** ,  
**NVME\_FEAT\_TT\_TMPTHH\_SHIFT** ,  
**NVME\_FEAT\_TT\_TMPTHH\_MASK** ,  
**NVME\_FEAT\_ERROR\_RECOVERY\_TLER\_SHIFT** ,  
**NVME\_FEAT\_ERROR\_RECOVERY\_TLER\_MASK** ,  
**NVME\_FEAT\_ERROR\_RECOVERY\_DULBE\_SHIFT** ,  
**NVME\_FEAT\_ERROR\_RECOVERY\_DULBE\_MASK** ,  
**NVME\_FEAT\_VWC\_WCE\_SHIFT** ,  
**NVME\_FEAT\_VWC\_WCE\_MASK** ,  
**NVME\_FEAT\_NRQS\_NSQR\_SHIFT** ,  
**NVME\_FEAT\_NRQS\_NSQR\_MASK** ,  
**NVME\_FEAT\_NRQS\_NCQR\_SHIFT** ,  
**NVME\_FEAT\_NRQS\_NCQR\_MASK** ,  
**NVME\_FEAT\_IRQC\_THR\_SHIFT** ,  
**NVME\_FEAT\_IRQC\_THR\_MASK** ,  
**NVME\_FEAT\_IRQC\_TIME\_SHIFT** ,  
**NVME\_FEAT\_IRQC\_TIME\_MASK** ,  
**NVME\_FEAT\_ICFG\_IV\_SHIFT** ,  
**NVME\_FEAT\_ICFG\_IV\_MASK** ,  
**NVME\_FEAT\_ICFG\_CD\_SHIFT** ,  
**NVME\_FEAT\_ICFG\_CD\_MASK** ,  
**NVME\_FEAT\_WA\_DN\_SHIFT** ,  
**NVME\_FEAT\_WA\_DN\_MASK** ,  
**NVME\_FEAT\_AE\_SMART\_SHIFT** ,  
**NVME\_FEAT\_AE\_SMART\_MASK** ,  
**NVME\_FEAT\_AE\_NAN\_SHIFT** ,  
**NVME\_FEAT\_AE\_NAN\_MASK** ,  
**NVME\_FEAT\_AE\_FW\_SHIFT** ,  
**NVME\_FEAT\_AE\_FW\_MASK** ,  
**NVME\_FEAT\_AE\_TELEM\_SHIFT** ,  
**NVME\_FEAT\_AE\_TELEM\_MASK** ,  
**NVME\_FEAT\_AE\_ANA\_SHIFT** ,  
**NVME\_FEAT\_AE\_ANA\_MASK** ,  
**NVME\_FEAT\_AE\_PLA\_SHIFT** ,  
**NVME\_FEAT\_AE\_PLA\_MASK** ,  
**NVME\_FEAT\_AE\_LBAS\_SHIFT** ,  
**NVME\_FEAT\_AE\_LBAS\_MASK** ,  
**NVME\_FEAT\_AE\_EGA\_SHIFT** ,  
**NVME\_FEAT\_AE\_EGA\_MASK** ,  
**NVME\_FEAT\_AE\_NNSSHDN\_SHIFT** ,  
**NVME\_FEAT\_AE\_NNSSHDN\_MASK** ,  
**NVME\_FEAT\_AE\_TTHRY\_SHIFT** ,  
**NVME\_FEAT\_AE\_TTHRY\_MASK** ,  
**NVME\_FEAT\_AE\_RASSN\_SHIFT** ,  
**NVME\_FEAT\_AE\_RASSN\_MASK** ,  
**NVME\_FEAT\_AE\_RGRP0\_SHIFT** ,  
**NVME\_FEAT\_AE\_RGRP0\_MASK** ,  
**NVME\_FEAT\_AE\_ANSAN\_SHIFT** ,  
**NVME\_FEAT\_AE\_ANSAN\_MASK** ,  
**NVME\_FEAT\_AE\_CCRCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_CCRCN\_MASK** ,  
**NVME\_FEAT\_AE\_LHCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_LHCN\_MASK** ,  
**NVME\_FEAT\_AE\_RLCCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_RLCCN\_MASK** ,  
**NVME\_FEAT\_AE\_ZDCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_ZDCN\_MASK** ,  
**NVME\_FEAT\_AE\_PMDRLPCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_PMDRLPCN\_MASK** ,  
**NVME\_FEAT\_AE\_ADLPCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_ADLPCN\_MASK** ,  
**NVME\_FEAT\_AE\_HDLPCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_HDLPCN\_MASK** ,  
**NVME\_FEAT\_AE\_DLPCN\_SHIFT** ,  
**NVME\_FEAT\_AE\_DLPCN\_MASK** ,  
**NVME\_FEAT\_APST\_APSTE\_SHIFT** ,  
**NVME\_FEAT\_APST\_APSTE\_MASK** ,  
**NVME\_FEAT\_HMEM\_EHM\_SHIFT** ,  
**NVME\_FEAT\_HMEM\_EHM\_MASK** ,  
**NVME\_FEAT\_KATO\_TIMEOUT\_SHIFT** ,  
**NVME\_FEAT\_KATO\_TIMEOUT\_MASK** ,  
**NVME\_FEAT\_HCTM\_TMT2\_SHIFT** ,  
**NVME\_FEAT\_HCTM\_TMT2\_MASK** ,  
**NVME\_FEAT\_HCTM\_TMT1\_SHIFT** ,  
**NVME\_FEAT\_HCTM\_TMT1\_MASK** ,  
**NVME\_FEAT\_NOPS\_NOPPME\_SHIFT** ,  
**NVME\_FEAT\_NOPS\_NOPPME\_MASK** ,  
**NVME\_FEAT\_RRL\_NVMSETID\_SHIFT** ,  
**NVME\_FEAT\_RRL\_NVMSETID\_MASK** ,  
**NVME\_FEAT\_RRL\_RRL\_SHIFT** ,  
**NVME\_FEAT\_RRL\_RRL\_MASK** ,  
**NVME\_FEAT\_PLM\_NVMSETID\_SHIFT** ,  
**NVME\_FEAT\_PLM\_NVMSETID\_MASK** ,  
**NVME\_FEAT\_PLM\_LPE\_SHIFT** ,  
**NVME\_FEAT\_PLM\_LPE\_MASK** ,  
**NVME\_FEAT\_PLMW\_WS\_SHIFT** ,  
**NVME\_FEAT\_PLMW\_WS\_MASK** ,  
**NVME\_FEAT\_LBAS\_LSIRI\_SHIFT** ,  
**NVME\_FEAT\_LBAS\_LSIRI\_MASK** ,  
**NVME\_FEAT\_LBAS\_LSIPI\_SHIFT** ,  
**NVME\_FEAT\_LBAS\_LSIPI\_MASK** ,  
**NVME\_FEAT\_SC\_NODRM\_SHIFT** ,  
**NVME\_FEAT\_SC\_NODRM\_MASK** ,  
**NVME\_FEAT\_EG\_ENDGID\_SHIFT** ,  
**NVME\_FEAT\_EG\_ENDGID\_MASK** ,  
**NVME\_FEAT\_EG\_EGCW\_SHIFT** ,  
**NVME\_FEAT\_EG\_EGCW\_MASK** ,  
**NVME\_FEAT\_FDPE\_PHNDL\_SHIFT** ,  
**NVME\_FEAT\_FDPE\_PHNDL\_MASK** ,  
**NVME\_FEAT\_FDPE\_NOET\_SHIFT** ,  
**NVME\_FEAT\_FDPE\_NOET\_MASK** ,  
**NVME\_FEAT\_SPM\_PBSLC\_SHIFT** ,  
**NVME\_FEAT\_SPM\_PBSLC\_MASK** ,  
**NVME\_FEAT\_HOSTID\_EXHID\_SHIFT** ,  
**NVME\_FEAT\_HOSTID\_EXHID\_MASK** ,  
**NVME\_FEAT\_RM\_REGPRE\_SHIFT** ,  
**NVME\_FEAT\_RM\_REGPRE\_MASK** ,  
**NVME\_FEAT\_RM\_RESREL\_SHIFT** ,  
**NVME\_FEAT\_RM\_RESREL\_MASK** ,  
**NVME\_FEAT\_RM\_RESPRE\_SHIFT** ,  
**NVME\_FEAT\_RM\_RESPRE\_MASK** ,  
**NVME\_FEAT\_RP\_PTPL\_SHIFT** ,  
**NVME\_FEAT\_RP\_PTPL\_MASK** ,  
**NVME\_FEAT\_WP\_WPS\_SHIFT** ,  
**NVME\_FEAT\_WP\_WPS\_MASK** ,  
**NVME\_FEAT\_IOCSP\_IOCSCI\_SHIFT** ,  
**NVME\_FEAT\_IOCSP\_IOCSCI\_MASK** ,  
**NVME\_FEAT\_SPINUP\_CONTROL\_SHIFT** ,  
**NVME\_FEAT\_SPINUP\_CONTROL\_MASK** ,  
**NVME\_FEAT\_PLS\_MODE\_SHIFT** ,  
**NVME\_FEAT\_PLS\_MODE\_MASK** ,  
**NVME\_FEAT\_PERFC\_ATTRI\_SHIFT** ,  
**NVME\_FEAT\_PERFC\_ATTRI\_MASK** ,  
**NVME\_FEAT\_PERFC\_RVSPA\_SHIFT** ,  
**NVME\_FEAT\_PERFC\_RVSPA\_MASK** ,  
**NVME\_FEAT\_PERFC\_ATTRTYP\_SHIFT** ,  
**NVME\_FEAT\_PERFC\_ATTRTYP\_MASK** ,  
**NVME\_FEAT\_FDP\_ENABLED\_SHIFT** ,  
**NVME\_FEAT\_FDP\_ENABLED\_MASK** ,  
**NVME\_FEAT\_FDP\_INDEX\_SHIFT** ,  
**NVME\_FEAT\_FDP\_INDEX\_MASK** ,  
**NVME\_FEAT\_FDP\_EVENTS\_ENABLE\_SHIFT** ,  
**NVME\_FEAT\_FDP\_EVENTS\_ENABLE\_MASK** ,  
**NVME\_FEAT\_HOST\_ID\_EXHID\_SHIFT** ,  
**NVME\_FEAT\_HOST\_ID\_EXHID\_MASK** ,  
**NVME\_FEAT\_BPWPC\_BP0WPS\_SHIFT** ,  
**NVME\_FEAT\_BPWPC\_BP0WPS\_MASK** ,  
**NVME\_FEAT\_BPWPC\_BP1WPS\_SHIFT** ,  
**NVME\_FEAT\_BPWPC\_BP1WPS\_MASK** ,  
**NVME\_FEAT\_SANITIZE\_NODRM\_SHIFT** ,  
**NVME\_FEAT\_SANITIZE\_NODRM\_MASK** ,  
**NVME\_FEAT\_RESP\_PTPL\_SHIFT** ,  
**NVME\_FEAT\_RESP\_PTPL\_MASK** ,  
**NVME\_FEAT\_CDP\_CHPS** ,  
**NVME\_FEAT\_CDP\_PERFS** ,  
**NVME\_FEAT\_CDP\_PERID\_SHIFT** ,  
**NVME\_FEAT\_CDP\_PERID\_MASK** ,  
**NVME\_FEAT\_CDP\_PMDSS** ,  
**NVME\_FEAT\_CDP\_PPSC** ,  
**NVME\_FEAT\_POWER\_LIMIT\_PLV\_SHIFT** ,  
**NVME\_FEAT\_POWER\_LIMIT\_PLV\_MASK** ,  
**NVME\_FEAT\_POWER\_LIMIT\_PLS\_SHIFT** ,  
**NVME\_FEAT\_POWER\_LIMIT\_PLS\_MASK** ,  
**NVME\_FEAT\_POWER\_THRESH\_PTV\_SHIFT** ,  
**NVME\_FEAT\_POWER\_THRESH\_PTV\_MASK** ,  
**NVME\_FEAT\_POWER\_THRESH\_PTS\_SHIFT** ,  
**NVME\_FEAT\_POWER\_THRESH\_PTS\_MASK** ,  
**NVME\_FEAT\_POWER\_THRESH\_PMTS\_SHIFT** ,  
**NVME\_FEAT\_POWER\_THRESH\_PMTS\_MASK** ,  
**NVME\_FEAT\_POWER\_THRESH\_EPT\_SHIFT** ,  
**NVME\_FEAT\_POWER\_THRESH\_EPT\_MASK** ,  
**NVME\_FEAT\_POWER\_MEAS\_ACT\_SHIFT** ,  
**NVME\_FEAT\_POWER\_MEAS\_ACT\_MASK** ,  
**NVME\_FEAT\_POWER\_MEAS\_PMTS\_SHIFT** ,  
**NVME\_FEAT\_POWER\_MEAS\_PMTS\_MASK** ,  
**NVME\_FEAT\_POWER\_MEAS\_SMT\_SHIFT** ,  
**NVME\_FEAT\_POWER\_MEAS\_SMT\_MASK** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_UVT\_SHIFT** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_UVT\_MASK** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_OVT\_SHIFT** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_OVT\_MASK** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_EVT** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_VSENS\_SHIFT** ,  
**NVME\_FEAT\_VOLTAGE\_THRESHOLD\_VSENS\_MASK** ,  
**NVME\_FEAT\_VOLTAGE\_MEASUREMENT\_ACT\_SHIFT** ,  
**NVME\_FEAT\_VOLTAGE\_MEASUREMENT\_ACT\_MASK** ,  
**NVME\_FEAT\_RATE\_LIMITING\_TID\_SHIFT** ,  
**NVME\_FEAT\_RATE\_LIMITING\_TID\_MASK** ,  
**NVME\_FEAT\_RATE\_LIMITING\_TGT\_SHIFT** ,  
**NVME\_FEAT\_RATE\_LIMITING\_TGT\_MASK**

};

# [Constants](#Constants)

[NVME\_FEAT\_ARBITRATION\_BURST\_SHIFT](#NVME_FEAT_ARBITRATION_BURST_SHIFT)

[NVME\_FEAT\_ARBITRATION\_BURST\_MASK](#NVME_FEAT_ARBITRATION_BURST_MASK)

[NVME\_FEAT\_ARBITRATION\_LPW\_SHIFT](#NVME_FEAT_ARBITRATION_LPW_SHIFT)

[NVME\_FEAT\_ARBITRATION\_LPW\_MASK](#NVME_FEAT_ARBITRATION_LPW_MASK)

[NVME\_FEAT\_ARBITRATION\_MPW\_SHIFT](#NVME_FEAT_ARBITRATION_MPW_SHIFT)

[NVME\_FEAT\_ARBITRATION\_MPW\_MASK](#NVME_FEAT_ARBITRATION_MPW_MASK)

[NVME\_FEAT\_ARBITRATION\_HPW\_SHIFT](#NVME_FEAT_ARBITRATION_HPW_SHIFT)

[NVME\_FEAT\_ARBITRATION\_HPW\_MASK](#NVME_FEAT_ARBITRATION_HPW_MASK)

[NVME\_FEAT\_PWRMGMT\_PS\_SHIFT](#NVME_FEAT_PWRMGMT_PS_SHIFT)

[NVME\_FEAT\_PWRMGMT\_PS\_MASK](#NVME_FEAT_PWRMGMT_PS_MASK)

[NVME\_FEAT\_PWRMGMT\_WH\_SHIFT](#NVME_FEAT_PWRMGMT_WH_SHIFT)

[NVME\_FEAT\_PWRMGMT\_WH\_MASK](#NVME_FEAT_PWRMGMT_WH_MASK)

[NVME\_FEAT\_PWRMGMT\_IIELL\_SHIFT](#NVME_FEAT_PWRMGMT_IIELL_SHIFT)

Shift amount to set/get the Idle I/O Exit Latency Limit (IIELL), in units of 100 microseconds

[NVME\_FEAT\_PWRMGMT\_IIELL\_MASK](#NVME_FEAT_PWRMGMT_IIELL_MASK)

Mask to set/get IIELL

[NVME\_FEAT\_LBAR\_NR\_SHIFT](#NVME_FEAT_LBAR_NR_SHIFT)

[NVME\_FEAT\_LBAR\_NR\_MASK](#NVME_FEAT_LBAR_NR_MASK)

[NVME\_FEAT\_TT\_TMPTH\_SHIFT](#NVME_FEAT_TT_TMPTH_SHIFT)

[NVME\_FEAT\_TT\_TMPTH\_MASK](#NVME_FEAT_TT_TMPTH_MASK)

[NVME\_FEAT\_TT\_TMPSEL\_SHIFT](#NVME_FEAT_TT_TMPSEL_SHIFT)

[NVME\_FEAT\_TT\_TMPSEL\_MASK](#NVME_FEAT_TT_TMPSEL_MASK)

[NVME\_FEAT\_TT\_THSEL\_SHIFT](#NVME_FEAT_TT_THSEL_SHIFT)

[NVME\_FEAT\_TT\_THSEL\_MASK](#NVME_FEAT_TT_THSEL_MASK)

[NVME\_FEAT\_TT\_TMPTHH\_SHIFT](#NVME_FEAT_TT_TMPTHH_SHIFT)

[NVME\_FEAT\_TT\_TMPTHH\_MASK](#NVME_FEAT_TT_TMPTHH_MASK)

[NVME\_FEAT\_ERROR\_RECOVERY\_TLER\_SHIFT](#NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT)

[NVME\_FEAT\_ERROR\_RECOVERY\_TLER\_MASK](#NVME_FEAT_ERROR_RECOVERY_TLER_MASK)

[NVME\_FEAT\_ERROR\_RECOVERY\_DULBE\_SHIFT](#NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT)

[NVME\_FEAT\_ERROR\_RECOVERY\_DULBE\_MASK](#NVME_FEAT_ERROR_RECOVERY_DULBE_MASK)

[NVME\_FEAT\_VWC\_WCE\_SHIFT](#NVME_FEAT_VWC_WCE_SHIFT)

[NVME\_FEAT\_VWC\_WCE\_MASK](#NVME_FEAT_VWC_WCE_MASK)

[NVME\_FEAT\_NRQS\_NSQR\_SHIFT](#NVME_FEAT_NRQS_NSQR_SHIFT)

[NVME\_FEAT\_NRQS\_NSQR\_MASK](#NVME_FEAT_NRQS_NSQR_MASK)

[NVME\_FEAT\_NRQS\_NCQR\_SHIFT](#NVME_FEAT_NRQS_NCQR_SHIFT)

[NVME\_FEAT\_NRQS\_NCQR\_MASK](#NVME_FEAT_NRQS_NCQR_MASK)

[NVME\_FEAT\_IRQC\_THR\_SHIFT](#NVME_FEAT_IRQC_THR_SHIFT)

[NVME\_FEAT\_IRQC\_THR\_MASK](#NVME_FEAT_IRQC_THR_MASK)

[NVME\_FEAT\_IRQC\_TIME\_SHIFT](#NVME_FEAT_IRQC_TIME_SHIFT)

[NVME\_FEAT\_IRQC\_TIME\_MASK](#NVME_FEAT_IRQC_TIME_MASK)

[NVME\_FEAT\_ICFG\_IV\_SHIFT](#NVME_FEAT_ICFG_IV_SHIFT)

[NVME\_FEAT\_ICFG\_IV\_MASK](#NVME_FEAT_ICFG_IV_MASK)

[NVME\_FEAT\_ICFG\_CD\_SHIFT](#NVME_FEAT_ICFG_CD_SHIFT)

[NVME\_FEAT\_ICFG\_CD\_MASK](#NVME_FEAT_ICFG_CD_MASK)

[NVME\_FEAT\_WA\_DN\_SHIFT](#NVME_FEAT_WA_DN_SHIFT)

[NVME\_FEAT\_WA\_DN\_MASK](#NVME_FEAT_WA_DN_MASK)

[NVME\_FEAT\_AE\_SMART\_SHIFT](#NVME_FEAT_AE_SMART_SHIFT)

[NVME\_FEAT\_AE\_SMART\_MASK](#NVME_FEAT_AE_SMART_MASK)

[NVME\_FEAT\_AE\_NAN\_SHIFT](#NVME_FEAT_AE_NAN_SHIFT)

[NVME\_FEAT\_AE\_NAN\_MASK](#NVME_FEAT_AE_NAN_MASK)

[NVME\_FEAT\_AE\_FW\_SHIFT](#NVME_FEAT_AE_FW_SHIFT)

[NVME\_FEAT\_AE\_FW\_MASK](#NVME_FEAT_AE_FW_MASK)

[NVME\_FEAT\_AE\_TELEM\_SHIFT](#NVME_FEAT_AE_TELEM_SHIFT)

[NVME\_FEAT\_AE\_TELEM\_MASK](#NVME_FEAT_AE_TELEM_MASK)

[NVME\_FEAT\_AE\_ANA\_SHIFT](#NVME_FEAT_AE_ANA_SHIFT)

[NVME\_FEAT\_AE\_ANA\_MASK](#NVME_FEAT_AE_ANA_MASK)

[NVME\_FEAT\_AE\_PLA\_SHIFT](#NVME_FEAT_AE_PLA_SHIFT)

[NVME\_FEAT\_AE\_PLA\_MASK](#NVME_FEAT_AE_PLA_MASK)

[NVME\_FEAT\_AE\_LBAS\_SHIFT](#NVME_FEAT_AE_LBAS_SHIFT)

[NVME\_FEAT\_AE\_LBAS\_MASK](#NVME_FEAT_AE_LBAS_MASK)

[NVME\_FEAT\_AE\_EGA\_SHIFT](#NVME_FEAT_AE_EGA_SHIFT)

[NVME\_FEAT\_AE\_EGA\_MASK](#NVME_FEAT_AE_EGA_MASK)

[NVME\_FEAT\_AE\_NNSSHDN\_SHIFT](#NVME_FEAT_AE_NNSSHDN_SHIFT)

[NVME\_FEAT\_AE\_NNSSHDN\_MASK](#NVME_FEAT_AE_NNSSHDN_MASK)

[NVME\_FEAT\_AE\_TTHRY\_SHIFT](#NVME_FEAT_AE_TTHRY_SHIFT)

[NVME\_FEAT\_AE\_TTHRY\_MASK](#NVME_FEAT_AE_TTHRY_MASK)

[NVME\_FEAT\_AE\_RASSN\_SHIFT](#NVME_FEAT_AE_RASSN_SHIFT)

[NVME\_FEAT\_AE\_RASSN\_MASK](#NVME_FEAT_AE_RASSN_MASK)

[NVME\_FEAT\_AE\_RGRP0\_SHIFT](#NVME_FEAT_AE_RGRP0_SHIFT)

[NVME\_FEAT\_AE\_RGRP0\_MASK](#NVME_FEAT_AE_RGRP0_MASK)

[NVME\_FEAT\_AE\_ANSAN\_SHIFT](#NVME_FEAT_AE_ANSAN_SHIFT)

[NVME\_FEAT\_AE\_ANSAN\_MASK](#NVME_FEAT_AE_ANSAN_MASK)

[NVME\_FEAT\_AE\_CCRCN\_SHIFT](#NVME_FEAT_AE_CCRCN_SHIFT)

[NVME\_FEAT\_AE\_CCRCN\_MASK](#NVME_FEAT_AE_CCRCN_MASK)

[NVME\_FEAT\_AE\_LHCN\_SHIFT](#NVME_FEAT_AE_LHCN_SHIFT)

[NVME\_FEAT\_AE\_LHCN\_MASK](#NVME_FEAT_AE_LHCN_MASK)

[NVME\_FEAT\_AE\_RLCCN\_SHIFT](#NVME_FEAT_AE_RLCCN_SHIFT)

Shift amount to get/set the Rate Limiting Configuration Change Notices (RLCCN)

[NVME\_FEAT\_AE\_RLCCN\_MASK](#NVME_FEAT_AE_RLCCN_MASK)

Mask to get/set RLCCN

[NVME\_FEAT\_AE\_ZDCN\_SHIFT](#NVME_FEAT_AE_ZDCN_SHIFT)

[NVME\_FEAT\_AE\_ZDCN\_MASK](#NVME_FEAT_AE_ZDCN_MASK)

[NVME\_FEAT\_AE\_PMDRLPCN\_SHIFT](#NVME_FEAT_AE_PMDRLPCN_SHIFT)

[NVME\_FEAT\_AE\_PMDRLPCN\_MASK](#NVME_FEAT_AE_PMDRLPCN_MASK)

[NVME\_FEAT\_AE\_ADLPCN\_SHIFT](#NVME_FEAT_AE_ADLPCN_SHIFT)

[NVME\_FEAT\_AE\_ADLPCN\_MASK](#NVME_FEAT_AE_ADLPCN_MASK)

[NVME\_FEAT\_AE\_HDLPCN\_SHIFT](#NVME_FEAT_AE_HDLPCN_SHIFT)

[NVME\_FEAT\_AE\_HDLPCN\_MASK](#NVME_FEAT_AE_HDLPCN_MASK)

[NVME\_FEAT\_AE\_DLPCN\_SHIFT](#NVME_FEAT_AE_DLPCN_SHIFT)

[NVME\_FEAT\_AE\_DLPCN\_MASK](#NVME_FEAT_AE_DLPCN_MASK)

[NVME\_FEAT\_APST\_APSTE\_SHIFT](#NVME_FEAT_APST_APSTE_SHIFT)

[NVME\_FEAT\_APST\_APSTE\_MASK](#NVME_FEAT_APST_APSTE_MASK)

[NVME\_FEAT\_HMEM\_EHM\_SHIFT](#NVME_FEAT_HMEM_EHM_SHIFT)

[NVME\_FEAT\_HMEM\_EHM\_MASK](#NVME_FEAT_HMEM_EHM_MASK)

[NVME\_FEAT\_KATO\_TIMEOUT\_SHIFT](#NVME_FEAT_KATO_TIMEOUT_SHIFT)

[NVME\_FEAT\_KATO\_TIMEOUT\_MASK](#NVME_FEAT_KATO_TIMEOUT_MASK)

[NVME\_FEAT\_HCTM\_TMT2\_SHIFT](#NVME_FEAT_HCTM_TMT2_SHIFT)

[NVME\_FEAT\_HCTM\_TMT2\_MASK](#NVME_FEAT_HCTM_TMT2_MASK)

[NVME\_FEAT\_HCTM\_TMT1\_SHIFT](#NVME_FEAT_HCTM_TMT1_SHIFT)

[NVME\_FEAT\_HCTM\_TMT1\_MASK](#NVME_FEAT_HCTM_TMT1_MASK)

[NVME\_FEAT\_NOPS\_NOPPME\_SHIFT](#NVME_FEAT_NOPS_NOPPME_SHIFT)

[NVME\_FEAT\_NOPS\_NOPPME\_MASK](#NVME_FEAT_NOPS_NOPPME_MASK)

[NVME\_FEAT\_RRL\_NVMSETID\_SHIFT](#NVME_FEAT_RRL_NVMSETID_SHIFT)

[NVME\_FEAT\_RRL\_NVMSETID\_MASK](#NVME_FEAT_RRL_NVMSETID_MASK)

[NVME\_FEAT\_RRL\_RRL\_SHIFT](#NVME_FEAT_RRL_RRL_SHIFT)

[NVME\_FEAT\_RRL\_RRL\_MASK](#NVME_FEAT_RRL_RRL_MASK)

[NVME\_FEAT\_PLM\_NVMSETID\_SHIFT](#NVME_FEAT_PLM_NVMSETID_SHIFT)

[NVME\_FEAT\_PLM\_NVMSETID\_MASK](#NVME_FEAT_PLM_NVMSETID_MASK)

[NVME\_FEAT\_PLM\_LPE\_SHIFT](#NVME_FEAT_PLM_LPE_SHIFT)

[NVME\_FEAT\_PLM\_LPE\_MASK](#NVME_FEAT_PLM_LPE_MASK)

[NVME\_FEAT\_PLMW\_WS\_SHIFT](#NVME_FEAT_PLMW_WS_SHIFT)

[NVME\_FEAT\_PLMW\_WS\_MASK](#NVME_FEAT_PLMW_WS_MASK)

[NVME\_FEAT\_LBAS\_LSIRI\_SHIFT](#NVME_FEAT_LBAS_LSIRI_SHIFT)

[NVME\_FEAT\_LBAS\_LSIRI\_MASK](#NVME_FEAT_LBAS_LSIRI_MASK)

[NVME\_FEAT\_LBAS\_LSIPI\_SHIFT](#NVME_FEAT_LBAS_LSIPI_SHIFT)

[NVME\_FEAT\_LBAS\_LSIPI\_MASK](#NVME_FEAT_LBAS_LSIPI_MASK)

[NVME\_FEAT\_SC\_NODRM\_SHIFT](#NVME_FEAT_SC_NODRM_SHIFT)

[NVME\_FEAT\_SC\_NODRM\_MASK](#NVME_FEAT_SC_NODRM_MASK)

[NVME\_FEAT\_EG\_ENDGID\_SHIFT](#NVME_FEAT_EG_ENDGID_SHIFT)

[NVME\_FEAT\_EG\_ENDGID\_MASK](#NVME_FEAT_EG_ENDGID_MASK)

[NVME\_FEAT\_EG\_EGCW\_SHIFT](#NVME_FEAT_EG_EGCW_SHIFT)

[NVME\_FEAT\_EG\_EGCW\_MASK](#NVME_FEAT_EG_EGCW_MASK)

[NVME\_FEAT\_FDPE\_PHNDL\_SHIFT](#NVME_FEAT_FDPE_PHNDL_SHIFT)

[NVME\_FEAT\_FDPE\_PHNDL\_MASK](#NVME_FEAT_FDPE_PHNDL_MASK)

[NVME\_FEAT\_FDPE\_NOET\_SHIFT](#NVME_FEAT_FDPE_NOET_SHIFT)

[NVME\_FEAT\_FDPE\_NOET\_MASK](#NVME_FEAT_FDPE_NOET_MASK)

[NVME\_FEAT\_SPM\_PBSLC\_SHIFT](#NVME_FEAT_SPM_PBSLC_SHIFT)

[NVME\_FEAT\_SPM\_PBSLC\_MASK](#NVME_FEAT_SPM_PBSLC_MASK)

[NVME\_FEAT\_HOSTID\_EXHID\_SHIFT](#NVME_FEAT_HOSTID_EXHID_SHIFT)

[NVME\_FEAT\_HOSTID\_EXHID\_MASK](#NVME_FEAT_HOSTID_EXHID_MASK)

[NVME\_FEAT\_RM\_REGPRE\_SHIFT](#NVME_FEAT_RM_REGPRE_SHIFT)

[NVME\_FEAT\_RM\_REGPRE\_MASK](#NVME_FEAT_RM_REGPRE_MASK)

[NVME\_FEAT\_RM\_RESREL\_SHIFT](#NVME_FEAT_RM_RESREL_SHIFT)

[NVME\_FEAT\_RM\_RESREL\_MASK](#NVME_FEAT_RM_RESREL_MASK)

[NVME\_FEAT\_RM\_RESPRE\_SHIFT](#NVME_FEAT_RM_RESPRE_SHIFT)

[NVME\_FEAT\_RM\_RESPRE\_MASK](#NVME_FEAT_RM_RESPRE_MASK)

[NVME\_FEAT\_RP\_PTPL\_SHIFT](#NVME_FEAT_RP_PTPL_SHIFT)

[NVME\_FEAT\_RP\_PTPL\_MASK](#NVME_FEAT_RP_PTPL_MASK)

[NVME\_FEAT\_WP\_WPS\_SHIFT](#NVME_FEAT_WP_WPS_SHIFT)

[NVME\_FEAT\_WP\_WPS\_MASK](#NVME_FEAT_WP_WPS_MASK)

[NVME\_FEAT\_IOCSP\_IOCSCI\_SHIFT](#NVME_FEAT_IOCSP_IOCSCI_SHIFT)

[NVME\_FEAT\_IOCSP\_IOCSCI\_MASK](#NVME_FEAT_IOCSP_IOCSCI_MASK)

[NVME\_FEAT\_SPINUP\_CONTROL\_SHIFT](#NVME_FEAT_SPINUP_CONTROL_SHIFT)

[NVME\_FEAT\_SPINUP\_CONTROL\_MASK](#NVME_FEAT_SPINUP_CONTROL_MASK)

[NVME\_FEAT\_PLS\_MODE\_SHIFT](#NVME_FEAT_PLS_MODE_SHIFT)

[NVME\_FEAT\_PLS\_MODE\_MASK](#NVME_FEAT_PLS_MODE_MASK)

[NVME\_FEAT\_PERFC\_ATTRI\_SHIFT](#NVME_FEAT_PERFC_ATTRI_SHIFT)

[NVME\_FEAT\_PERFC\_ATTRI\_MASK](#NVME_FEAT_PERFC_ATTRI_MASK)

[NVME\_FEAT\_PERFC\_RVSPA\_SHIFT](#NVME_FEAT_PERFC_RVSPA_SHIFT)

[NVME\_FEAT\_PERFC\_RVSPA\_MASK](#NVME_FEAT_PERFC_RVSPA_MASK)

[NVME\_FEAT\_PERFC\_ATTRTYP\_SHIFT](#NVME_FEAT_PERFC_ATTRTYP_SHIFT)

[NVME\_FEAT\_PERFC\_ATTRTYP\_MASK](#NVME_FEAT_PERFC_ATTRTYP_MASK)

[NVME\_FEAT\_FDP\_ENABLED\_SHIFT](#NVME_FEAT_FDP_ENABLED_SHIFT)

[NVME\_FEAT\_FDP\_ENABLED\_MASK](#NVME_FEAT_FDP_ENABLED_MASK)

[NVME\_FEAT\_FDP\_INDEX\_SHIFT](#NVME_FEAT_FDP_INDEX_SHIFT)

[NVME\_FEAT\_FDP\_INDEX\_MASK](#NVME_FEAT_FDP_INDEX_MASK)

[NVME\_FEAT\_FDP\_EVENTS\_ENABLE\_SHIFT](#NVME_FEAT_FDP_EVENTS_ENABLE_SHIFT)

[NVME\_FEAT\_FDP\_EVENTS\_ENABLE\_MASK](#NVME_FEAT_FDP_EVENTS_ENABLE_MASK)

[NVME\_FEAT\_HOST\_ID\_EXHID\_SHIFT](#NVME_FEAT_HOST_ID_EXHID_SHIFT)

[NVME\_FEAT\_HOST\_ID\_EXHID\_MASK](#NVME_FEAT_HOST_ID_EXHID_MASK)

[NVME\_FEAT\_BPWPC\_BP0WPS\_SHIFT](#NVME_FEAT_BPWPC_BP0WPS_SHIFT)

[NVME\_FEAT\_BPWPC\_BP0WPS\_MASK](#NVME_FEAT_BPWPC_BP0WPS_MASK)

[NVME\_FEAT\_BPWPC\_BP1WPS\_SHIFT](#NVME_FEAT_BPWPC_BP1WPS_SHIFT)

[NVME\_FEAT\_BPWPC\_BP1WPS\_MASK](#NVME_FEAT_BPWPC_BP1WPS_MASK)

[NVME\_FEAT\_SANITIZE\_NODRM\_SHIFT](#NVME_FEAT_SANITIZE_NODRM_SHIFT)

[NVME\_FEAT\_SANITIZE\_NODRM\_MASK](#NVME_FEAT_SANITIZE_NODRM_MASK)

[NVME\_FEAT\_RESP\_PTPL\_SHIFT](#NVME_FEAT_RESP_PTPL_SHIFT)

[NVME\_FEAT\_RESP\_PTPL\_MASK](#NVME_FEAT_RESP_PTPL_MASK)

[NVME\_FEAT\_CDP\_CHPS](#NVME_FEAT_CDP_CHPS)

Change Personality Settings (Set Features Command Dword 13 only)

[NVME\_FEAT\_CDP\_PERFS](#NVME_FEAT_CDP_PERFS)

Personality Freeze State (Set Features Command Dword 13, and Get Features Completion Queue Entry Dword 0)

[NVME\_FEAT\_CDP\_PERID\_SHIFT](#NVME_FEAT_CDP_PERID_SHIFT)

Shift amount to set/get the Personality Identifier (Set Features Command Dword 13, and Get Features Completion Queue Entry Dword 0)

[NVME\_FEAT\_CDP\_PERID\_MASK](#NVME_FEAT_CDP_PERID_MASK)

Mask to set/get the Personality Identifier

[NVME\_FEAT\_CDP\_PMDSS](#NVME_FEAT_CDP_PMDSS)

Personality Manufacturing Default Settings State (Get Features Completion Queue Entry Dword 0 only)

[NVME\_FEAT\_CDP\_PPSC](#NVME_FEAT_CDP_PPSC)

Pending Personality Settings Change (Get Features Completion Queue Entry Dword 0 only)

[NVME\_FEAT\_POWER\_LIMIT\_PLV\_SHIFT](#NVME_FEAT_POWER_LIMIT_PLV_SHIFT)

[NVME\_FEAT\_POWER\_LIMIT\_PLV\_MASK](#NVME_FEAT_POWER_LIMIT_PLV_MASK)

[NVME\_FEAT\_POWER\_LIMIT\_PLS\_SHIFT](#NVME_FEAT_POWER_LIMIT_PLS_SHIFT)

[NVME\_FEAT\_POWER\_LIMIT\_PLS\_MASK](#NVME_FEAT_POWER_LIMIT_PLS_MASK)

[NVME\_FEAT\_POWER\_THRESH\_PTV\_SHIFT](#NVME_FEAT_POWER_THRESH_PTV_SHIFT)

[NVME\_FEAT\_POWER\_THRESH\_PTV\_MASK](#NVME_FEAT_POWER_THRESH_PTV_MASK)

[NVME\_FEAT\_POWER\_THRESH\_PTS\_SHIFT](#NVME_FEAT_POWER_THRESH_PTS_SHIFT)

[NVME\_FEAT\_POWER\_THRESH\_PTS\_MASK](#NVME_FEAT_POWER_THRESH_PTS_MASK)

[NVME\_FEAT\_POWER\_THRESH\_PMTS\_SHIFT](#NVME_FEAT_POWER_THRESH_PMTS_SHIFT)

[NVME\_FEAT\_POWER\_THRESH\_PMTS\_MASK](#NVME_FEAT_POWER_THRESH_PMTS_MASK)

[NVME\_FEAT\_POWER\_THRESH\_EPT\_SHIFT](#NVME_FEAT_POWER_THRESH_EPT_SHIFT)

[NVME\_FEAT\_POWER\_THRESH\_EPT\_MASK](#NVME_FEAT_POWER_THRESH_EPT_MASK)

[NVME\_FEAT\_POWER\_MEAS\_ACT\_SHIFT](#NVME_FEAT_POWER_MEAS_ACT_SHIFT)

[NVME\_FEAT\_POWER\_MEAS\_ACT\_MASK](#NVME_FEAT_POWER_MEAS_ACT_MASK)

[NVME\_FEAT\_POWER\_MEAS\_PMTS\_SHIFT](#NVME_FEAT_POWER_MEAS_PMTS_SHIFT)

[NVME\_FEAT\_POWER\_MEAS\_PMTS\_MASK](#NVME_FEAT_POWER_MEAS_PMTS_MASK)

[NVME\_FEAT\_POWER\_MEAS\_SMT\_SHIFT](#NVME_FEAT_POWER_MEAS_SMT_SHIFT)

[NVME\_FEAT\_POWER\_MEAS\_SMT\_MASK](#NVME_FEAT_POWER_MEAS_SMT_MASK)

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_UVT\_SHIFT](#NVME_FEAT_VOLTAGE_THRESHOLD_UVT_SHIFT)

Shift amount to set/get the Undervoltage Threshold (UVT)

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_UVT\_MASK](#NVME_FEAT_VOLTAGE_THRESHOLD_UVT_MASK)

Mask to set/get UVT

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_OVT\_SHIFT](#NVME_FEAT_VOLTAGE_THRESHOLD_OVT_SHIFT)

Shift amount to set/get the Overvoltage Threshold (OVT)

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_OVT\_MASK](#NVME_FEAT_VOLTAGE_THRESHOLD_OVT_MASK)

Mask to set/get OVT

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_EVT](#NVME_FEAT_VOLTAGE_THRESHOLD_EVT)

Enable Voltage Threshold

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_VSENS\_SHIFT](#NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_SHIFT)

Shift amount to set/get the Voltage Sensor Select (VSENS), see *enum nvme\_voltage\_sensor*

[NVME\_FEAT\_VOLTAGE\_THRESHOLD\_VSENS\_MASK](#NVME_FEAT_VOLTAGE_THRESHOLD_VSENS_MASK)

Mask to set/get VSENS

[NVME\_FEAT\_VOLTAGE\_MEASUREMENT\_ACT\_SHIFT](#NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_SHIFT)

Shift amount to set the Action (ACT), see *enum* *nvme\_voltage\_measurement\_act*

[NVME\_FEAT\_VOLTAGE\_MEASUREMENT\_ACT\_MASK](#NVME_FEAT_VOLTAGE_MEASUREMENT_ACT_MASK)

Mask to set ACT

[NVME\_FEAT\_RATE\_LIMITING\_TID\_SHIFT](#NVME_FEAT_RATE_LIMITING_TID_SHIFT)

Shift amount to set/get the Target Identifier (TID)

[NVME\_FEAT\_RATE\_LIMITING\_TID\_MASK](#NVME_FEAT_RATE_LIMITING_TID_MASK)

Mask to set/get TID

[NVME\_FEAT\_RATE\_LIMITING\_TGT\_SHIFT](#NVME_FEAT_RATE_LIMITING_TGT_SHIFT)

Shift amount to set/get the Target (TGT), see *enum nvme\_rate\_limiting\_target*

[NVME\_FEAT\_RATE\_LIMITING\_TGT\_MASK](#NVME_FEAT_RATE_LIMITING_TGT_MASK)

Mask to set/get TGT

enum nvme\_feat October 2026

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Document: nvme_feat-libnvme3(2) from nvme-cli 3.2-r0 (Chainguard OS)
Source: https://github.com/linux-nvme/nvme-cli